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? 2013 microchip technology inc. preliminary ds41674b-page 1 high-performance risc cpu: ? c compiler optimized architecture ? only 49 instructions ? 2k words linear program memory addressing ? 256 bytes linear data memory addressing ? operating speed: - dc ? 32 mhz clock input - dc ? 125 ns instruction cycle ? interrupt capability with automatic context saving ? 16-level deep hardware stack with optional overflow/underflow reset ? direct, indirect and relative addressing modes: - two full 16-bit file select registers (fsrs) - fsrs can read program and data memory flexible oscillator structure: ? 16 mhz internal oscillator block: - factory calibrated to 1%, typical - software selectable frequency range from 32 mhz to 31 khz ? 4x phase-lock loop (pll), usable with 16 mhz internal oscillator - allows 32 mhz software selectable clock frequency ? 31 khz low-power internal oscillator ? three external clock modes up to 20 mhz special microcontroller features: ? operating voltage range: - 1.8v to 3.6v ? self-programmable under software control ? power-on reset (por) ? power-up timer (pwrt) ? programmable low-power brown-out reset (lpbor) ? extended watchdog timer (wdt): - programmable period from 1 ms to 256s ? programmable code protection ? in-circuit serial programming? (icsp?) via two pins ? enhanced low-voltage programming (lvp) ? power-saving sleep mode: - low-power sleep mode - low-power bor (lpbor) ? integrated temperature indicator ? 128 bytes high-endurance flash: - 100,000 write flash endurance (minimum) low-power features: ? standby current: - 20 na @ 1.8v, typical ? watchdog timer current: - 200 na @ 1.8v, typical ? operating current: -30 ? a/mhz @ 1.8v, typical peripheral features: ? analog-to-digital converter (adc): - 10-bit resolution - 5 external channels - 2 internal channels: - fixed voltage reference - temperature indicator channel - auto acquisition capability - conversion available during sleep - special event triggers - conversion available during sleep ? hardware capacitive voltage divider (cvd) - double sample conversions - two result registers - inverted acquisition - 7-bit pre-charge timer - 7-bit acquisition timer - two guard ring output drives - adjustable sample and hold capacitor array ? voltage reference module: - fixed voltage reference (fvr) with 1.024v and 2.048v output levels ? 6 i/o pins (1 input-only pin): - high current sink/source 25 ma/25 ma - individually programmable weak pull-ups - individually programmable interrupt-on-change (ioc) pins ? timer0: 8-bit timer/counter with 8-bit programmable prescaler ? master synchronous serial port (mssp) with spi and i 2 c tm with: - 7-bit address masking - smbus/pmbus tm compatibility 8-pin flash, 8-bit microcontrollers PIC12LF1552
PIC12LF1552 ds41674b-page 2 preliminary ? 2013 microchip technology inc. PIC12LF1552 device data sheet index program memory flash (words) data sram (bytes) i/o?s (2) 10-bit adc (ch) timers (8-bit) mssp (i 2 c?/spi) debug (1) PIC12LF1552 (1) 2048 256 6 5 1 1 h note 1: i - debugging, integrated on chip; h - debugging, available using debug header. 2: one pin is input-only. data sheet index: (unshaded devices are described in this document.) 1: ds41674 PIC12LF1552 data sheet, 8-pin flash, 8-bit microcontrollers. note: for other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office.
? 2013 microchip technology inc. preliminary ds41674b-page 3 PIC12LF1552 figure 1: 8-pin pdip, soic, ms op, dfn diagram, PIC12LF1552 table 1: 8-pin a llocation table i/o 8-pin pdip/soic/msop/dfn adc/hardware cvd reference timer mssp interrupt pull-up basic ra0 7 an0 ? ? sdo (1) ss (2) ioc y icspdat ra1 6 an1 v ref + ? sck scl ioc y icspclk ra2 5 an2 adout ? t0cki sdi (1) sda (1) int ioc y ? ra3 4 ? ? ? ss (1) sda (2) sdi (2) ioc y mclr v pp ra4 3 an3 adgrda ? ? sdo (2) ioc y clkout ra5 2 an4 adgrdb ? ? ? ioc y clkin v dd 1 ? ? ? ? ? ? v dd v ss 8? ? ? ? ?? v ss note 1: default location for peripheral pin function. alternat e location can be selected using the apfcon register. 2: alternate location for peripheral pin function selected by the apfcon register. pdip, soic, msop, dfn note: see ta b l e 1 for location of all peripheral functions. 1 2 3 4 8 7 6 5 v dd ra5 ra4 mclr /v pp /ra3 v ss ra0/icspdat ra1/icspclk ra2 PIC12LF1552
PIC12LF1552 ds41674b-page 4 preliminary ? 2013 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 7 2.0 enhanced mid-range cpu ...................................................................................................... .................................................. 11 3.0 memory organization ......................................................................................................... ........................................................ 13 4.0 device configuration ........................................................................................................ .......................................................... 35 5.0 oscillator module........................................................................................................... ............................................................. 41 6.0 resets ...................................................................................................................... .................................................................. 49 7.0 interrupts .................................................................................................................. .................................................................. 57 8.0 power-down mode (sleep) ..................................................................................................... ................................................... 69 9.0 watchdog timer (wdt) ........................................................................................................ ..................................................... 71 10.0 flash program memory control ............................................................................................... .................................................. 75 11.0 i/o ports .................................................................................................................. ................................................................... 91 12.0 interrupt-on-change ........................................................................................................ .......................................................... 97 13.0 fixed voltage reference (fvr) .............................................................................................. ................................................. 101 14.0 temperature indicator module ............................................................................................... .................................................. 103 15.0 analog-to-digital converter (adc) module ................................................................................... ........................................... 105 16.0 hardware capacitive voltage divider (cvd) module ........................................................................... .................................... 119 17.0 timer0 module .............................................................................................................. ........................................................... 138 18.0 master synchronous serial port module ...................................................................................... ............................................ 143 19.0 in-circuit serial programming? (icsp?) ..................................................................................... .......................................... 197 20.0 instruction set summary .................................................................................................... ...................................................... 199 21.0 electrical specifications.................................................................................................. .......................................................... 213 22.0 dc and ac characteristics graphs and charts ................................................................................ ....................................... 231 23.0 development support........................................................................................................ ....................................................... 233 24.0 packaging information...................................................................................................... ........................................................ 237 appendix a: data sheet revision history........................................................................................ .................................................. 248 index .......................................................................................................................... ........................................................................ 250 the microchip web site ......................................................................................................... ............................................................ 254 customer change notification service ........................................................................................... ................................................... 254 customer support ............................................................................................................... ............................................................... 254 reader response ................................................................................................................ .............................................................. 255 product identification system.................................................................................................. ........................................................... 257
? 2013 microchip technology inc. preliminary ds41674b-page 5 PIC12LF1552 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
PIC12LF1552 ds41674b-page 6 preliminary ? 2013 microchip technology inc. notes:
? 2013 microchip technology inc. preliminary ds41674b-page 7 PIC12LF1552 1.0 device overview the PIC12LF1552 are described within this data sheet. they are available in 8-pin packages. figure 1-1 shows a block diagram of the PIC12LF1552 devices. ta b l e 1 - 2 shows the pinout descriptions. reference tab l e 1 - 1 for peripherals available per device. table 1-1: device peripheral summary peripheral PIC12LF1552 analog-to-digital converter (adc) hardware capacitor voltage divider (cvd) fixed voltage reference (fvr) temperature indicator master synchronous serial ports mssp1 timers timer0
PIC12LF1552 ds41674b-page 8 preliminary ? 2013 microchip technology inc. figure 1-1: PIC12LF1552 block diagram note 1: see applicable chapters for more information on peripherals. 2: see table 1-1 for peripherals available on specific devices. cpu program flash memory ram timing generation intrc oscillator mclr ( figure 2-1 ) timer0 porta adc 10-bit fvr te m p . indicator clkin clkout mssp
? 2013 microchip technology inc. preliminary ds41674b-page 9 PIC12LF1552 table 1-2: PIC12LF1552 pinout description name function input type output type description ra0/an0/sdo (1) /ss (2) / icspdat ra0 ttl cmos general purpose i/o. an0 an ? adc channel input. sdo ? cmos spi data output. ss st ? slave select input. icspdat st cmos icsp? data i/o. ra1/an1/v ref +/sck/scl/ icspclk ra1 ttl cmos general purpose i/o. an1 an ? adc channel input. v ref + an ? adc positive voltage reference input. sck st cmos spi clock. scl i 2 codi 2 c? clock. icspclk st ? icsp? programming clock. ra2/an2/adout/t0cki/ sdi (1) /sda (1) /int ra2 st cmos general purpose i/o. an2 an ? adc channel input. adout cmos ? adc with cvd output. t0cki st ? timer0 clock input. sdi st ? spi data input. sda i 2 codi 2 c? data input/output. int st ? external interrupt. ra3/mclr/ v pp /ss (1) /sdi (2) / sda (2) ra3 ttl ? general purpose input. mclr st ? master clear with internal pull-up. v pp hv ? programming voltage. ss st ? slave select input. sdi st ? spi data input. sda i 2 codi 2 c? data input/output. ra4/an3/sdo (2) /clkout/ adgrda ra4 ttl cmos general purpose i/o. an3 an ? adc channel input. sdo ? cmos spi data output. clkout ? cmos f osc /4 output. adgrda ? cmos guard ring output a. ra5/an4/clkin/adgrdb ra5 ttl cmos general purpose i/o. an4 an ? adc channel input. clkin cmos ? external clock input (ec mode). adgrdb ? cmos guard ring output b. v dd v dd power ? positive supply. v ss v ss power ? ground reference. legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c? = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: default location for peripheral pin function. alternat e location can be selected using the apfcon register. 2: alternate location for peripheral pin function selected by the apfcon register.
PIC12LF1552 ds41674b-page 10 preliminary ? 2013 microchip technology inc. notes:
? 2013 microchip technology inc. preliminary ds41674b-page 11 PIC12LF1552 2.0 enhanced mid-range cpu this family of devices contain an enhanced mid-range 8-bit cpu core. the cpu has 49 instructions. interrupt capability includes automatic context saving. the hardware stack is 16 levels deep and has overflow and underflow reset capability. direct, indirect, and relative addressing modes are available. two file select registers (fsrs) provide the ability to read program and data memory. ? automatic interrupt context saving ? 16-level stack with overflow and underflow ? file select registers ? instruction set figure 2-1: core block diagram data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 12 addr mux fsr reg status reg mux alu instruction decode & control timing generation clkin clkout 8 8 12 3 internal oscillator block configuration data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 addr mux fsr reg status reg mux alu w reg instruction decode & control timing generation 8 8 3 internal oscillator block configuration 15 data bus 8 14 program bus instruction reg program counter 16-level stack (15-bit) direct addr 7 ram addr addr mux indirect addr fsr0 reg status reg mux alu instruction decode and control timing generation 8 8 3 internal oscillator block configuration flash program memory ram fsr reg fsr reg fsr1 reg 15 15 mux 15 program memory read (pmr) 12 fsr reg fsr reg bsr reg 5 power-up timer power-on reset watchdog timer v dd brown-out reset v ss v dd v ss v dd v ss
PIC12LF1552 ds41674b-page 12 preliminary ? 2013 microchip technology inc. 2.1 automatic interrupt context saving during interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. this saves stack space and user code. see section 7.5 ?automatic context saving? , for more information. 2.2 16-level stack with overflow and underflow these devices have an external stack memory 15 bits wide and 16 words deep. a stack overflow or under- flow will set the appropriate bit (stkovf or stkunf) in the pcon register and, if enabled, will cause a soft- ware reset. see section section 3.5 ?stack? for more details. 2.3 file select registers there are two 16-bit file select registers (fsr). fsrs can access all file registers and program memory, which allows one data pointer for all memory. when an fsr points to program memory, there is one additional instruction cycle in instructions using indf to allow the data to be fetched. general purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. there are also new instructions to support the fsrs. see section 3.6 ?indirect addressing? for more details. 2.4 instruction set there are 49 instructions for the enhanced mid-range cpu to support the features of the cpu. see section 20.0 ?instruction set summary? for more details.
? 2013 microchip technology inc. preliminary ds41674b-page 13 PIC12LF1552 3.0 memory organization these devices contain the following types of memory: ? program memory - configuration words - device id -user id - flash program memory ? data memory - core registers - special function registers - general purpose ram - common ram the following features are associated with access and control of program memory and data memory: ? pcl and pclath ?stack ? indirect addressing 3.1 program memory organization the enhanced mid-range core has a 15-bit program counter capable of addressing a 32k x 14 program memory space. table 3-1 shows the memory sizes implemented. accessing a location above these boundaries will cause a wrap-around within the implemented memory space. the reset vector is at 0000h and the interrupt vector is at 0004h (see figure 3-1 ). table 3-1: device sizes and addresses device program memory space (words) last program memory address high-endurance flash memory address range (1) PIC12LF1552 2,048 07ffh 0780h-07ffh note 1: high-endurance flash applies to the low byte of each address in the range.
PIC12LF1552 ds41674b-page 14 preliminary ? 2013 microchip technology inc. figure 3-1: program memory map and stack for PIC12LF1552 3.1.1 reading program memory as data there are two methods of accessing constants in program memory. the first method is to use tables of retlw instructions. the second method is to set an fsr to point to the program memory. 3.1.1.1 retlw instruction the retlw instruction can be used to provide access to tables of constants. the recommended way to create such a table is shown in example 3-1 . example 3-1: retlw instruction the brw instruction makes this type of table very sim- ple to implement. if your code must remain portable with previous generations of microcontrollers, then the brw instruction is not available so the older table read method must be used. pc<14:0> 15 0000h 0004h stack level 0 stack level 15 reset vector interrupt vector stack level 1 0005h on-chip program memory page 0 7fffh wraps to page 0 wraps to page 0 wraps to page 0 0800h call , callw return , retlw interrupt, retfie rollover to page 0 rollover to page 0 7fffh constants brw ;add index in w to ;program counter to ;select data retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ;? lots of code? movlw data_index call constants ;? the constant is in w
? 2013 microchip technology inc. preliminary ds41674b-page 15 PIC12LF1552 3.1.1.2 indirect read with fsr the program memory can be accessed as data by setting bit 7 of the fsrxh register and reading the matching indfx register. the moviw instruction will place the lower 8 bits of the addressed word in the w register. writes to the program memory cannot be performed via the indf registers. instructions that access the program memory via the fsr require one extra instruction cycle to complete. example 3-2 demonstrates accessing the program memory via an fsr. the high directive will set bit<7> if a label points to a location in program memory. example 3-2: accessing program memory via fsr 3.2 data memory organization the data memory is partitioned into 32 memory banks with 128 bytes in a bank. each bank consists of ( figure 3-2 ): ? 12 core registers ? 20 special function registers (sfr) ? up to 80 bytes of general purpose ram (gpr) ? 16 bytes of common ram the active bank is selected by writing the bank number into the bank select register (bsr). unimplemented memory will read as ? 0 ?. all data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two file select registers (fsr). see section 3.6 ?indirect addressing? for more information. data memory uses a 12-bit address. the upper 7 bits of the address define the bank address and the lower 5 bits select the registers/ram in that bank. 3.2.1 core registers the core registers contain the registers that directly affect the basic operation. the core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0bh/x8bh). these registers are listed below in ta b l e 3 - 2 . for detailed information, see tab l e 3 - 5 . table 3-2: core registers constants retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ;? lots of code? movlw low constants movwf fsr1l movlw high constants movwf fsr1h moviw 0[fsr1] ;the program memory is in w addresses bankx x00h or x80h indf0 x01h or x81h indf1 x02h or x82h pcl x03h or x83h status x04h or x84h fsr0l x05h or x85h fsr0h x06h or x86h fsr1l x07h or x87h fsr1h x08h or x88h bsr x09h or x89h wreg x0ah or x8ah pclath x0bh or x8bh intcon
PIC12LF1552 ds41674b-page 16 preliminary ? 2013 microchip technology inc. 3.2.1.1 status register the status register, shown in register 3-1 , contains: ? the arithmetic status of the alu ? the reset status the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as ? 000u u1uu ? (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect any status bits. for other instructions not affecting any status bits (refer to section 20.0 ?instruction set summary? ). 3.3 register definitions: status note 1: the c and dc bits operate as borrow and digit borrow out bits, respectively, in subtraction. register 3-1: status: status register u-0 u-0 u-0 r-1/q r-1/q r/w-0/u r/w-0/u r/w-0/u ? ? ? to pd zdc (1) c (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7-5 unimplemented: read as ? 0 ? bit 4 to : time-out bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/digit borrow bit ( addwf , addlw , sublw , subwf instructions) (1) 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/borrow bit (1) ( addwf , addlw , sublw , subwf instructions) (1) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
? 2013 microchip technology inc. preliminary ds41674b-page 17 PIC12LF1552 3.3.1 special function register the special function registers are registers used by the application to control the desired operation of peripheral functions in the device. the special function registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0ch/x8ch through x1fh/x9fh). the registers associated with the operation of the peripherals are described in the appro- priate peripheral chapter of this data sheet. 3.3.2 general purpose ram there are up to 80 bytes of gpr in each data memory bank. the special function registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0ch/x8ch through x1fh/x9fh). 3.3.2.1 linear access to gpr the general purpose ram can be accessed in a non-banked method via the fsrs. this can simplify access to large memory structures. see section 3.6.2 ?linear data memory? for more information. 3.3.3 common ram there are 16 bytes of common ram accessible from all banks. figure 3-2: banked memory partitioning 3.3.4 device memory maps the memory maps for PIC12LF1552 are as shown in table 3-3 . 0bh 0ch 1fh 20h 6fh 70h 7fh 00h common ram (16 bytes) general purpose ram (80 bytes maximum) core registers (12 bytes) special function registers (20 bytes maximum) memory region 7-bit bank offset
PIC12LF1552 ds41674b-page 18 preliminary ? 2013 microchip technology inc. table 3-3: PIC12LF1552 memory map bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 000h core registers ( ta b l e 3 - 2 ) 080h core registers ( ta b l e 3 - 2 ) 100h core registers ( table 3-2 ) 180h core registers ( table 3-2 ) 200h core registers ( table 3-2 ) 280h core registers ( table 3-2 ) 300h core registers ( table 3-2 ) 380h core registers ( table 3-2 ) 00bh 08bh 10bh 18bh 20bh 28bh 30bh 38bh 00ch porta 08ch trisa 10ch lata 18ch ansela 20ch wpua 28ch ? 30ch ? 38ch ? 00dh ? 08dh ? 10dh ? 18dh ? 20dh ? 28dh ? 30dh ? 38dh ? 00eh ?08eh ?10eh ?18eh ?20eh ?28eh ?30eh ?38eh ? 00fh ?08fh ?10fh ?18fh ?20fh ?28fh ?30fh ?38fh ? 010h ?090h ?110h ?190h ?210h ?290h ? 310h ? 390h ? 011h pir1 091h pie1 111h ? 191h pmadrl 211h sspbuf 291h ? 311h ? 391h iocap 012h pir2 092h pie2 112h ? 192h pmadrh 212h sspadd 292h ? 312h ? 392h iocan 013h ?093h ?113h ? 193h pmdatl 213h sspmsk 293h ? 313h ? 393h iocaf 014h ?094h ?114h ? 194h pmdath 214h sspstat 294h ? 314h ? 394h ? 015h tmr0 095h option_reg 115h ? 195h pmcon1 215h sspcon1 295h ? 315h ? 395h ? 016h ? 096h pcon 116h borcon 196h pmcon2 216h sspcon2 296h ? 316h ? 396h ? 017h ? 097h wdtcon 117h fvrcon 197h ?217h sspcon3 297h ? 317h ? 397h ? 018h ? 098h ?118h ? 198h ?218h ? 298h ? 318h ? 398h ? 019h ? 099h osccon 119h ? 199h ? 219h ?299h ? 319h ? 399h ? 01ah ? 09ah oscstat 11ah ?19ah ? 21ah ?29ah ?31ah ?39ah ? 01bh ? 09bh adresl (1) 11bh ?19bh ? 21bh ?29bh ?31bh ? 39bh ? 01ch ? 09ch adresh (1) 11ch ? 19ch ? 21ch ? 29ch ? 31ch ? 39ch ? 01dh ? 09dh adcon0 (1) 11dh apfcon 19dh ? 21dh ? 29dh ? 31dh ? 39dh ? 01eh ? 09eh adcon1 (1) 11eh ? 19eh ? 21eh ? 29eh ? 31eh ? 39eh ? 01fh ? 09fh adcon2 (1) 11fh ?19fh ? 21fh ? 29fh ? 31fh ? 39fh ? 020h general purpose register 48 bytes 0a0h general purpose register 80 bytes 120h general purpose register 80 bytes 1a0h unimplemented read as ? 0 ? 220h unimplemented read as ? 0 ? 2a0h unimplemented read as ? 0 ? 320h unimplemented read as ? 0 ? 3a0h unimplemented read as ? 0 ? 0efh 16fh 1efh 26fh 2efh 36fh 3efh 0f0h common ram (accesses 70h ? 7fh) 170h common ram (accesses 70h ? 7fh) 1f0h accesses 70h ? 7fh 270h accesses 70h ? 7fh 2f0h accesses 70h ? 7fh 370h accesses 70h ? 7fh 3f0h accesses 70h ? 7fh 07fh 0ffh 17fh 1ffh 27fh 2ffh 37fh 3ffh legend: = unimplemented data memory locations, read as ? 0 ? note 1: these adc registers are the same as the registers in bank 14.
? 2013 microchip technology inc. preliminary ds41674b-page 19 PIC12LF1552 table 3-3: PIC12LF1552 memory map (continued) bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 bank 14 bank 15 400h 40bh core registers ( ta b l e 3 - 2 ) 480h 48bh core registers ( ta b l e 3 - 2 ) 500h 50bh core registers ( table 3-2 ) 580h 58bh core registers ( table 3-2 ) 600h 60bh core registers ( table 3-2 ) 680h 68bh core registers ( table 3-2 ) 700h 70bh core registers ( table 3-2 ) 780h 78bh core registers ( table 3-2 ) 40ch ? 48ch ? 50ch ? 58ch ? 60ch ? 68ch ? 70ch ? 78ch ? 40dh ? 48dh ? 50dh ? 58dh ? 60dh ? 68dh ? 70dh ? 78dh ? 40eh ?48eh ?50eh ?58eh ?60eh ?68eh ?70eh ?78eh ? 40fh ?48fh ?50fh ?58fh ?60fh ?68fh ?70fh ?78fh ? 410h ?490h ?510h ?590h ?610h ?690h ? 710h ? 790h ? 411h ?491h ?511h ?591h ?611h ?691h ? 711h aadcon0 (1) 791h ? 412h ?492h ?512h ?592h ?612h ?692h ? 712h aadcon1 (1) 792h ? 413h ?493h ?513h ?593h ?613h ?693h ? 713h aadcon2 (1) 793h ? 414h ?494h ?514h ?594h ?614h ?694h ? 714h aadcon3 794h ? 415h ?495h ?515h ?595h ?615h ?695h ? 715h aadstat 795h ? 416h ?496h ?516h ?596h ?616h ?696h ? 716h aadpre 796h ? 417h ?497h ?517h ?597h ?617h ?697h ? 717h aadacq 797h ? 418h ?498h ?518h ?598h ?618h ?698h ? 718h aadgrd 798h ? 419h ?499h ?519h ?599h ?619h ?699h ? 719h aadcap 799h ? 41ah ?49ah ?51ah ?59ah ?61ah ?69ah ?71ahaadres0l (1) 79ah ? 41bh ?49bh ?51bh ?59bh ?61bh ?69bh ? 71bh aadres0h (1) 79bh ? 41ch ? 49ch ? 51ch ? 59ch ? 61ch ? 69ch ? 71ch aadres1l 79ch ? 41dh ? 49dh ? 51dh ? 59dh ? 61dh ? 69dh ? 71dh aadres1h 79dh ? 41eh ?49eh ?51eh ?59eh ?61eh ?69eh ?71eh ?79eh ? 41fh ?49fh ?51fh ?59fh ?61fh ?69fh ?71fh ?79fh ? 420h unimplemented read as ? 0 ? 4a0h unimplemented read as ? 0 ? 520h unimplemented read as ? 0 ? 5a0h unimplemented read as ? 0 ? 620h unimplemented read as ? 0 ? 6a0h unimplemented read as ? 0 ? 720h unimplemented read as ? 0 ? 7a0h unimplemented read as ? 0 ? 46fh 4efh 56fh 5efh 66fh 6efh 76fh 7efh 470h accesses 70h ? 7fh 4f0h accesses 70h ? 7fh 570h accesses 70h ? 7fh 5f0h accesses 70h ? 7fh 670h accesses 70h ? 7fh 6f0h accesses 70h ? 7fh 770h accesses 70h ? 7fh 7f0h accesses 70h ? 7fh 47fh 4ffh 57fh 5ffh 67fh 6ffh 77fh 7ffh bank 16 bank 17 bank 18 bank 19 bank 20 bank 21 bank 22 bank 23 800h 80bh core registers ( ta b l e 3 - 2 ) 880h 88bh core registers ( ta b l e 3 - 2 ) 900h 90bh core registers ( table 3-2 ) 980h 98bh core registers ( table 3-2 ) a00h a0bh core registers ( table 3-2 ) a80h a8bh core registers ( table 3-2 ) b00h b0bh core registers ( table 3-2 ) b80h b8bh core registers ( table 3-2 ) 80ch unimplemented read as ? 0 ? 88ch unimplemented read as ? 0 ? 90ch unimplemented read as ? 0 ? 98ch unimplemented read as ? 0 ? a0ch unimplemented read as ? 0 ? a8ch unimplemented read as ? 0 ? b0ch unimplemented read as ? 0 ? b8ch unimplemented read as ? 0 ? 86fh 8efh 96fh 9efh a6fh aefh b6fh befh 870h accesses 70h ? 7fh 8f0h accesses 70h ? 7fh 970h accesses 70h ? 7fh 9f0h accesses 70h ? 7fh a70h accesses 70h ? 7fh af0h accesses 70h ? 7fh b70h accesses 70h ? 7fh bf0h accesses 70h ? 7fh 87fh 8ffh 97fh 9ffh a7fh affh b7fh bffh legend: = unimplemented data memory locations, read as ? 0 ? note 1: these adc registers are the same as the registers in bank 1.
PIC12LF1552 ds41674b-page 20 preliminary ? 2013 microchip technology inc. table 3-3: PIC12LF1552 memory map (continued) legend: = unimplemented data memory locations, read as ? 0 ?. bank 24 bank 25 bank 26 bank 27 bank 28 bank 29 bank 30 bank 31 c00h c0bh core registers ( ta b l e 3 - 2 ) c80h c8bh core registers ( ta b l e 3 - 2 ) d00h d0bh core registers ( ta b l e 3 - 2 ) d80h d8bh core registers ( ta b l e 3 - 2 ) e00h e0bh core registers ( ta b l e 3 - 2 ) e80h e8bh core registers ( ta b l e 3 - 2 ) f00h f0bh core registers ( ta b l e 3 - 2 ) f80h f8bh core registers ( ta b l e 3 - 2 ) c0ch ?c8ch ?d0ch ?d8ch ?e0ch ?e8ch ?f0ch ?f8ch see ta b l e 3 - 4 for register mapping details c0dh ?c8dh ?d0dh ?d8dh ?e0dh ?e8dh ?f0dh ?f8dh c0eh ?c8eh ?d0eh ?d8eh ?e0eh ?e8eh ?f0eh ?f8eh c0fh ?c8fh ?d0fh ?d8fh ?e0fh ?e8fh ?f0fh ?f8fh c10h ?c90h ?d10h ?d90h ?e10h ?e90h ?f10h ?f90h c11h ?c91h ?d11h ?d91h ?e11h ?e91h ?f11h ?f91h c12h ?c92h ?d12h ?d92h ?e12h ?e92h ?f12h ?f92h c13h ?c93h ?d13h ?d93h ?e13h ?e93h ?f13h ?f93h c14h ?c94h ?d14h ?d94h ?e14h ?e94h ?f14h ?f94h c15h ?c95h ?d15h ?d95h ?e15h ?e95h ?f15h ?f95h c16h ?c96h ?d16h ?d96h ?e16h ?e96h ?f16h ?f96h c17h ?c97h ?d17h ?d97h ?e17h ?e97h ?f17h ?f97h c18h ?c98h ?d18h ?d98h ?e18h ?e98h ?f18h ?f98h c19h ?c99h ?d19h ?d99h ?e19h ?e99h ?f19h ?f99h c1ah ?c9ah ?d1ah ?d9ah ?e1ah ?e9ah ?f1ah ?f9ah c1bh ?c9bh ?d1bh ?d9bh ?e1bh ?e9bh ?f1bh ?f9bh c1ch ?c9ch ?d1ch ?d9ch ?e1ch ?e9ch ?f1ch ?f9ch c1dh ?c9dh ?d1dh ?d9dh ?e1dh ?e9dh ?f1dh ?f9dh c1eh ?c9eh ?d1eh ?d9eh ?e1eh ?e9eh ?f1eh ?f9eh c1fh ?c9fh ?d1fh ?d9fh ?e1fh ?e9fh ?f1fh ?f9fh c20h unimplemented read as ? 0 ? ca0h unimplemented read as ? 0 ? d20h unimplemented read as ? 0 ? da0h unimplemented read as ? 0 ? e20h unimplemented read as ? 0 ? ea0h unimplemented read as ? 0 ? f20h unimplemented read as ? 0 ? fa0h c6fh cefh d6fh defh e6fh eefh f6fh fefh c70h accesses 70h ? 7fh cf0h accesses 70h ? 7fh d70h accesses 70h ? 7fh df0h accesses 70h ? 7fh e70h accesses 70h ? 7fh ef0h accesses 70h ? 7fh f70h accesses 70h ? 7fh ff0h accesses 70h ? 7fh cffh cffh d7fh dffh e7fh effh f7fh fffh
? 2013 microchip technology inc. preliminary ds41674b-page 21 PIC12LF1552 table 3-4: PIC12LF1552 memory map detail (bank 31) bank 31 f8ch fe3h unimplemented read as ? 0 ? fe4h status_shad fe5h wreg_shad fe6h bsr_shad fe7h pclath_shad fe8h fsr0l_shad fe9h fsr0h_shad feah fsr1l_shad febh fsr1h_shad fech ? fedh stkptr feeh tosl fefh tosh legend: = unimplemented data memory locations, read as ? 0 ?.
PIC12LF1552 ds41674b-page 22 preliminary ? 2013 microchip technology inc. 3.3.5 core function registers summary the core function registers listed in ta bl e 3 - 5 can be addressed from any bank. table 3-5: core funct ion registers summary addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets bank 0-31 x00h or x80h indf0 addressing this location uses contents of fsr0h/fsr0l to address data memory (not a physical register) xxxx xxxx uuuu uuuu x01h or x81h indf1 addressing this location uses contents of fsr1h/fsr1l to address data memory (not a physical register) xxxx xxxx uuuu uuuu x02h or x82h pcl program counter (pc) least significant byte 0000 0000 0000 0000 x03h or x83h status ? ? ?to pd zdcc ---1 1000 ---q quuu x04h or x84h fsr0l indirect data memory address 0 low pointer 0000 0000 uuuu uuuu x05h or x85h fsr0h indirect data memory address 0 high pointer 0000 0000 0000 0000 x06h or x86h fsr1l indirect data memory address 1 low pointer 0000 0000 uuuu uuuu x07h or x87h fsr1h indirect data memory address 1 high pointer 0000 0000 0000 0000 x08h or x88h bsr ? ? ?bsr<4:0> ---0 0000 ---0 0000 x09h or x89h wreg working register 0000 0000 uuuu uuuu x0ah or x8ah pclath ? write buffer for the upper 7 bits of the program counter -000 0000 -000 0000 x0bh or x8bh intcon gie peie tmr0ie inte iocie tmr0if intf iocif 0000 0000 0000 0000 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?.
? 2013 microchip technology inc. preliminary ds41674b-page 23 PIC12LF1552 table 3-6: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets bank 0 00ch porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --xx xxxx --xx xxxx 00eh to 010h ? unimplemented ? ? 011h pir1 ?adif ? ?sspif ? ? ? -0-- 0--- -0-- 0--- 012h pir2 ? ? ? ?bclif ? ? ? ---- 0--- ---- 0--- 013h ? unimplemented ? ? 014h ? unimplemented ? ? 015h tmr0 holding register for the 8-bit timer0 count xxxx xxxx uuuu uuuu 016h to 01fh ? unimplemented ? ? bank 1 08ch trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 --11 1111 --11 1111 08dh ? unimplemented ? ? 08eh ? unimplemented ? ? 08fh ? unimplemented ? ? 090h ? unimplemented ? ? 091h pie1 ?adie ? ? sspie ? ? ? -0-- 0--- -0-- 0--- 092h pie2 ? ? ? ?bclie ? ? ? ---- 0--- ---- 0--- 093h ? unimplemented ? ? 094h ? unimplemented ? ? 095h option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 1111 1111 1111 1111 096h pcon stkovf stkunf ?rwdt rmclr ri por bor 00-1 11qq qq-q qquu 097h wdtcon ? ? wdtps<4:0> swdten --01 0110 --01 0110 098h ? unimplemented ? ? 099h osccon spllen ircf<3:0> ?scs<1:0> 0011 1-00 0011 1-00 09ah oscstat ?pllr ?hfiofr ? ? lfiofr hfiofs -0-0 --00 -q-q --qq 09bh adresl (2) adc result register 0 low xxxx xxxx uuuu uuuu 09ch adresh (2) adc result register 0 high xxxx xxxx uuuu uuuu 09dh adcon0 (2) ? chs<4:0> go/done adon -000 0000 -000 0000 09eh adcon1 (2) adfm adcs<2:0> ? ? adpref<1:0> 0000 --00 0000 --00 09fh adcon2 (2) trigsel<3:0> ? ? ? ? 0000 ---- 0000 ---- bank 2 10ch lata ? ?lata5lata4 ? lata2 lata1 lata0 --xx -xxx --uu -uuu 10dh to 115h ? unimplemented ? ? 116h borcon sboren borfs ? ? ? ? ? borrdy 10-- ---q uu-- ---u 117h fvrcon fvren fvrrdy tsen tsrng ? ?adfvr<1:0> 0q00 --00 0q00 --00 118h to 11ch ? unimplemented ? ? 11dh apfcon ? sdosel sssel sdsel ? ? ? ? -000 ---- -000 ---- 11eh ? ? ? 11fh ? unimplemented ? ? legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: unimplemented, read as ? 1 ?. 2: this register is available in bank 1 and bank 14 under similar register names. see section 16.1.11 ?hardware cvd register mapping? .
PIC12LF1552 ds41674b-page 24 preliminary ? 2013 microchip technology inc. bank 3 18ch ansela ? ? ansa5 ansa4 ? ansa2 ansa1 ansa0 --11 -111 --11 -111 18dh ? unimplemented ? ? 18eh ? unimplemented ? ? 18fh ? unimplemented ? ? 190h ? unimplemented ? ? 191h pmadrl flash program memory address register low byte 0000 0000 0000 0000 192h pmadrh ? (1) flash program memory address register high byte 1000 0000 1000 0000 193h pmdatl flash program memory read data register low byte xxxx xxxx uuuu uuuu 194h pmdath ? ? flash program memory read data register high byte --xx xxxx --uu uuuu 195h pmcon1 ? (1) cfgs lwlo free wrerr wren wr rd 0000 x000 0000 q000 196h pmcon2 flash program memory control register 2 0000 0000 0000 0000 197h to 19fh ? unimplemented ? ? bank 4 20ch wpua ? ? wpua5 wpua4 wpua3 wpua2 wpua1 wpua0 --11 1111 --11 1111 20dh to 210h ? unimplemented ? ? 211h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 212h sspadd add<7:0> 0000 0000 0000 0000 213h sspmsk msk<7:0> 1111 1111 1111 1111 214h sspstat smp cke d/a psr/w ua bf 0000 0000 0000 0000 215h sspcon1 wcol sspov sspen ckp sspm<3:0> 0000 0000 0000 0000 216h sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 217h sspcon3 acktim pcie scie boen sdaht sbcde ahen dhen 0000 0000 0000 0000 218h to 21fh ? unimplemented ? ? bank 5 28ch to 29fh ? unimplemented ? ? bank 6 30ch to 31fh ? unimplemented ? ? table 3-6: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: unimplemented, read as ? 1 ?. 2: this register is available in bank 1 and bank 14 under similar register names. see section 16.1.11 ?hardware cvd register mapping? .
? 2013 microchip technology inc. preliminary ds41674b-page 25 PIC12LF1552 bank 7 38ch to 390h ? unimplemented ? ? 391h iocap ? ? iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 --00 0000 --00 0000 392h iocan ? ? iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 --00 0000 --00 0000 393h iocaf ? ? iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 --00 0000 --00 0000 394h to 39fh ? unimplemented ? ? bank 8-13 x0ch/ x8ch ? x1fh/ x9fh ? unimplemented ? ? bank 14 70ch to 710h ? unimplemented ? ? 711h aadcon0 (2) ? chs<4:0> go/done adon -000 0000 -000 0000 712h aadcon1 (2) adfm adcs<2:0> ? ? adpref<1:0> 0000 --00 0000 --00 713h aadcon2 (2) ? trigsel<2:0> ? ? ? ? -000 ---- -000 ---- 714h aadcon3 adeppol adippol ? adoen adooen ? adipen addsen 0000 0-00 0000 0-00 715h aadstat ? ? ? ? ? adconv adstg<1:0> ---- -000 ---- -000 716h aadpre ? adpre<6:0> -000 0000 -000 0000 717h aadacq ? adacq<6:0> -000 0000 -000 0000 718h aadgrd grdboe grdaoe grdpol ? ? ? ? ? 000- ---- 000- ---- 719h aadcap ? ? ? ? ? adcap<2:0> ---- -000 ---- -000 71ah aadres0l (2) adc result register 0 low xxxx xxxx uuuu uuuu 71bh aadres0h (2) adc result register 0 high xxxx xxxx uuuu uuuu 71ch aadres1l (2) adc result register 1 low xxxx xxxx uuuu uuuu 71dh aadres1h (2) adc result register 1 high xxxx xxxx uuuu uuuu 71eh ? unimplemented ? ? 71fh ? unimplemented ? ? table 3-6: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: unimplemented, read as ? 1 ?. 2: this register is available in bank 1 and bank 14 under similar register names. see section 16.1.11 ?hardware cvd register mapping? .
PIC12LF1552 ds41674b-page 26 preliminary ? 2013 microchip technology inc. banks 15-30 x0ch/ x8ch ? x1fh/ x9fh ? unimplemented ? ? bank 31 f8ch ? fe3h ? unimplemented ? ? fe4h status_ shad ? ? ? ? ? z_shad dc_shad c_shad ---- -xxx ---- -uuu fe5h wreg_ shad working register shadow xxxx xxxx uuuu uuuu fe6h bsr_ shad ? ? ? bank select register shadow ---x xxxx ---u uuuu fe7h pclath_ shad ? program counter latch high register shadow -xxx xxxx uuuu uuuu fe8h fsr0l_ shad indirect data memory address 0 low pointer shadow xxxx xxxx uuuu uuuu fe9h fsr0h_ shad indirect data memory address 0 high pointer shadow xxxx xxxx uuuu uuuu feah fsr1l_ shad indirect data memory address 1 low pointer shadow xxxx xxxx uuuu uuuu febh fsr1h_ shad indirect data memory address 1 high pointer shadow xxxx xxxx uuuu uuuu fech ? unimplemented ? ? fedh stkptr ? ? ? current stack pointer ---1 1111 ---1 1111 feeh tosl top-of-stack low byte xxxx xxxx uuuu uuuu fefh tosh ? top-of-stack high byte -xxx xxxx -uuu uuuu table 3-6: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: unimplemented, read as ? 1 ?. 2: this register is available in bank 1 and bank 14 under similar register names. see section 16.1.11 ?hardware cvd register mapping? .
? 2013 microchip technology inc. preliminary ds41674b-page 27 PIC12LF1552 3.4 pcl and pclath the program counter (pc) is 15 bits wide. the low byte comes from the pcl register, which is a readable and writable register. the high byte (pc<14:8>) is not directly readable or writable and comes from pclath. on any reset, the pc is cleared. figure 3-3 shows the five situations for the loading of the pc. figure 3-3: loading of pc in different situations 3.4.1 modifying pcl executing any instruction with the pcl register as the destination simultaneously causes the program coun- ter pc<14:8> bits (pch) to be replaced by the contents of the pclath register. this allows the entire contents of the program counter to be changed by writing the desired upper 7 bits to the pclath register. when the lower 8 bits are written to the pcl register, all 15 bits of the program counter will change to the values con- tained in the pclath register and those being written to the pcl register. 3.4.2 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when performing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). refer to application note an556, ?implementing a table read? (ds00556). 3.4.3 computed function calls a computed function call allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. when performing a table read using a computed function call , care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). if using the call instruction, the pch<2:0> and pcl registers are loaded with the operand of the call instruction. pch<6:3> is loaded with pclath<6:3>. the callw instruction enables computed calls by com- bining pclath and w to form the destination address. a computed callw is accomplished by loading the w register with the desired address and executing callw . the pcl register is loaded with the value of w and pch is loaded with pclath. 3.4.4 branching the branching instructions add an offset to the pc. this allows relocatable code and code that crosses page boundaries. there are two forms of branching, brw and bra . the pc will have incremented to fetch the next instruction in both cases. when using either branching instruction, a pcl memory boundary may be crossed. if using brw , load the w register with the desired unsigned address and execute brw . the entire pc will be loaded with the address pc + 1 + w. if using bra , the entire pc will be loaded with pc + 1 +, the signed value of the operand of the bra instruction. pcl pch 0 14 pc 0 6 7 alu result 8 pclath pcl pch 0 14 pc 0 6 4 opcode <10:0> 11 pclath pcl pch 0 14 pc 0 6 7 w 8 pclath instruction with pcl as destination goto, call callw pcl pch 0 14 pc pc + w 15 brw pcl pch 0 14 pc pc + opcode <8:0> 15 bra
PIC12LF1552 ds41674b-page 28 preliminary ? 2013 microchip technology inc. 3.5 stack all devices have a 16-level x 15-bit wide hardware stack (refer to figures 3-4 through 3-7 ). the stack space is not part of either program or data space. the pc is pushed onto the stack when call or callw instructions are executed or an interrupt causes a branch. the stack is poped in the event of a return , retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer if the stvren bit is programmed to ? 0 ? (configuration words). this means that after the stack has been pushed sixteen times, the seventeenth push overwrites the value that was stored from the first push. the eighteenth push overwrites the second push (and so on). the stkovf and stkunf flag bits will be set on an over- flow/underflow, regardless of whether the reset is enabled. 3.5.1 accessing the stack the stack is available through the tosh, tosl and stkptr registers. stkptr is the current value of the stack pointer. tosh:tosl register pair points to the top of the stack. both registers are read/writable. tos is split into tosh and tosl due to the 15-bit size of the pc. to access the stack, adjust the value of stkptr, which will position tosh:tosl, then read/write to tosh:tosl. stkptr is 5 bits to allow detection of overflow and underflow. during normal program operation, call, callw and interrupts will increment stkptr while retlw , return , and retfie will decrement stkptr. at any time, stkptr can be inspected to see how much stack is left. the stkptr always points at the currently used place on the stack. therefore, a call or callw will increment the stkptr and then write the pc, and a return will unload the pc and then decrement the stkptr. reference figure 3-4 through figure 3-7 for examples of accessing the stack. figure 3-4: accessing the stack example 1 note 1: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, callw , return , retlw and retfie instructions or the vectoring to an interrupt address. note: care should be taken when modifying the stkptr while interrupts are enabled. 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 0x0000 stkptr = 0x1f initial stack configuration: after reset, the stack is empty. the empty stack is initialized so the stack pointer is pointing at 0x1f. if the stack overflow/underflow reset is enabled, the tosh/tosl registers will return ? 0 ?. if the stack overflow/underflow reset is disabled, the tosh/tosl registers will return the contents of stack address 0x0f. 0x1f stkptr = 0x1f stack reset disabled (stvren = 0 ) stack reset enabled (stvren = 1 ) tosh:tosl tosh:tosl
? 2013 microchip technology inc. preliminary ds41674b-page 29 PIC12LF1552 figure 3-5: accessing the stack example 2 figure 3-6: accessing the stack example 3 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 return address 0x00 stkptr = 0x00 this figure shows the stack configuration after the first call or a single interrupt. if a return instruction is executed, the return addre ss will be placed in the program counter and the stack pointer decremented to the empty state (0x1f). tosh:tosl 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 return address 0x06 return address 0x05 return address 0x04 return address 0x03 return address 0x02 return address 0x01 return address 0x00 stkptr = 0x06 after seven call s or six call s and an interrupt, the stack looks like the figure on the left. a series of return instructions will repeatedly place the return addresses into the program counter and pop the stack. tosh:tosl
PIC12LF1552 ds41674b-page 30 preliminary ? 2013 microchip technology inc. figure 3-7: accessing the stack example 4 3.5.2 overflow/underflow reset if the stvren bit in configuration words is programmed to ? 1 ?, the device will be reset if the stack is pushed beyond the sixteenth level or poped beyond the first level, setting the appropriate bits (stkovf or stkunf, respectively) in the pcon register. 3.6 indirect addressing the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the file select registers (fsr). if the fsrn address specifies one of the two indfn registers, the read will return ? 0 ? and the write will not occur (though status bits may be affected). the fsrn register value is created by the pair fsrnh and fsrnl. the fsr registers form a 16-bit address that allows an addressing space with 65536 locations. these locations are divided into three memory regions: ? traditional data memory ? linear data memory ? program flash memory 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 return address 0x00 stkptr = 0x10 when the stack is full, the next call or an interrupt will set the stack pointer to 0x10. this is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. if the stack overflow/underflow reset is enabled, a reset will occur and location 0x00 will not be overwritten. return address return address return address return address return address return address return address return address return address return address return address return address return address return address return address tosh:tosl
? 2013 microchip technology inc. preliminary ds41674b-page 31 PIC12LF1552 figure 3-8: indirect addressing 0x0000 0x0fff traditional fsr address range data memory 0x1000 reserved linear data memory reserved 0x2000 0x29af 0x29b0 0x7fff 0x8000 0xffff 0x0000 0x0fff 0x0000 0x7fff program flash memory note: not all memory regions are completely implemented. consult device memory tables for memory limits. 0x1fff
PIC12LF1552 ds41674b-page 32 preliminary ? 2013 microchip technology inc. 3.6.1 traditional data memory the traditional data memory is a region from fsr address 0x000 to fsr address 0xfff. the addresses correspond to the absolute addresses of all sfr, gpr and common registers. figure 3-9: traditio nal data memory map indirect addressing direct addressing bank select location select 4bsr 6 0 from opcode fsrxl 70 bank select location select 00000 00001 00010 11111 0x00 0x7f bank 0 bank 1 bank 2 bank 31 0 fsrxh 70 0000
? 2013 microchip technology inc. preliminary ds41674b-page 33 PIC12LF1552 3.6.2 linear data memory the linear data memory is the region from fsr address 0x2000 to fsr address 0x29af. this region is a virtual region that points back to the 80-byte blocks of gpr memory in all the banks. unimplemented memory reads as 0x00. use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the fsr beyond one bank will go directly to the gpr memory of the next bank. the 16 bytes of common memory are not included in the linear data memory region. figure 3-10: linear data memory map 3.6.3 program flash memory to make constant data access easier, the entire program flash memory is mapped to the upper half of the fsr address space. when the msb of fsrnh is set, the lower 15 bits are the address in program memory which will be accessed through indf. only the lower 8 bits of each memory location is accessible via indf. writing to the program flash memory cannot be accomplished via the fsr/indf interface. all instructions that access program flash memory via the fsr/indf interface will require one additional instruction cycle to complete. figure 3-11: program flash memory map 7 0 1 7 0 0 location select 0x2000 fsrnh fsrnl 0x020 bank 0 0x06f 0x0a0 bank 1 0x0ef 0x120 bank 2 0x16f 0xf20 bank 30 0xf6f 0x29af 0 7 1 7 0 0 location select 0x8000 fsrnh fsrnl 0x0000 0x7fff 0xffff program flash memory (low 8 bits)
PIC12LF1552 ds41674b-page 34 preliminary ? 2013 microchip technology inc. notes:
? 2013 microchip technology inc. preliminary ds41674b-page 35 PIC12LF1552 4.0 device configuration device configuration consists of configuration words, code protection and device id. 4.1 configuration words there are several configuration word bits that allow different oscillator and memory protection options. these are implemented as configuration word 1 at 8007h and configuration word 2 at 8008h.
PIC12LF1552 ds41674b-page 36 preliminary ? 2013 microchip technology inc. 4.2 register definitions: configuration words register 4-1: config1: configuration word 1 u-1 u-1 r/p-1 r/p-1 r/p-1 u-1 ? ? clkouten boren<1:0> ? bit 13 bit 8 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 u-1 r/p-1 r/p-1 cp mclre pwrte wdte<1:0> ? fosc<1:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?1? ?0? = bit is cleared ?1? = bit is set -n = value when blank or after bulk erase bit 13-12 unimplemented: read as ? 1 ? bit 11 clkouten : clock out enable bit 1 = clkout function is disabled. i/o function on the clkout pin 0 = clkout function is enabled on the clkout pin bit 10-9 boren<1:0>: brown-out reset enable bits (1) 11 = bor enabled 10 = bor enabled during operation and disabled in sleep 01 = bor controlled by sboren bit of the borcon register 00 = bor disabled bit 8 unimplemented: read as ? 1 ? bit 7 cp : code protection bit (2) 1 = program memory code protection is disabled 0 = program memory code protection is enabled bit 6 mclre: mclr /v pp pin function select bit if lvp bit = 1 : this bit is ignored. if lvp bit = 0 : 1 =mclr /v pp pin function is mclr ; weak pull-up enabled. 0 =mclr /v pp pin function is digital input; mclr internally disabled; weak pull-up under control of wpue3 bit. bit 5 pwrte : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 4-3 wdte<1:0>: watchdog timer enable bits 11 = wdt enabled 10 = wdt enabled while running and disabled in sleep 01 = wdt controlled by the swdten bit in the wdtcon register 00 = wdt disabled bit 2 unimplemented: read as ? 1 ? bit 1-0 fosc<1:0>: oscillator selection bits 11 = ech: external clock, high-power mode: on clkin pin 10 = ecm: external clock, medium-power mode: on clkin pin 01 = ecl: external clock, low-power mode: on clkin pin 00 = intosc oscillator: i/o function on clkin pin note 1: enabling brown-out reset does not automatically enable power-up timer. 2: once enabled, code-protect can only be disabled by bulk erasing the device.
? 2013 microchip technology inc. preliminary ds41674b-page 37 PIC12LF1552 register 4-2: config2: configuration word 2 r/p-1 u-1 r/p-1 r/p-1 r/p-1 u-1 lvp ?lpbor borv stvren ? bit 13 bit 8 u-1u-1u-1u-1u-1u-1r/p-1r/p-1 ? ? ? ? ? ?wrt<1:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?1? ?0? = bit is cleared ?1? = bit is set -n = value when blank or after bulk erase bit 13 lvp: low-voltage programming enable bit (1) 1 = low-voltage programming enabled 0 = high-voltage on mclr must be used for programming bit 12 unimplemented: read as ? 1 ? bit 11 lpbor : low-power bor enable bit 1 = low-power brown-out reset is disabled 0 = low-power brown-out reset is enabled bit 10 borv: brown-out reset voltage selection bit (2) 1 = brown-out reset voltage ( vbor ), low trip point selected 0 = brown-out reset voltage ( vbor ), high trip point selected bit 9 stvren: stack overflow/underflow reset enable bit 1 = stack overflow or underflow will cause a reset 0 = stack overflow or underflow will not cause a reset bit 8-2 unimplemented: read as ? 1 ? bit 1-0 wrt<1:0>: flash memory self-write protection bits 2 kw flash memory : 11 = write protection off 10 = 000h to 1ffh write-protected, 200h to 7ffh may be modified 01 = 000h to 3ffh write-protected, 400h to 7ffh may be modified 00 = 000h to 7ffh write-protected, no addresses may be modified note 1: the lvp bit cannot be programmed to ? 0 ? when programming mode is entered via lvp. 2: see vbor parameter for specific trip point voltages.
PIC12LF1552 ds41674b-page 38 preliminary ? 2013 microchip technology inc. 4.3 code protection code protection allows the device to be protected from unauthorized access. internal access to the program memory is unaffected by any code protection setting. 4.3.1 program memory protection the entire program memory space is protected from external reads and writes by the cp bit in configuration words. when cp = 0 , external reads and writes of program memory are inhibited and a read will return all ? 0 ?s. the cpu can continue to read program memory, regardless of the protection bit settings. writing the program memory is dependent upon the write protection setting. see section 4.4 ?write protection? for more information. 4.4 write protection write protection allows the device to be protected from unintended self-writes. applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. the wrt<1:0> bits in configuration words define the size of the program memory block that is protected. 4.5 user id four memory locations (8000h-8003h) are designated as id locations where the user can store checksum or other code identification numbers. these locations are readable and writable during normal execution. see section 10.4 ?user id, device id and configuration word access? for more information on accessing these memory locations. for more information on checksum calculation, see the ? PIC12LF1552 memory programming specification ? (ds41642).
? 2013 microchip technology inc. preliminary ds41674b-page 39 PIC12LF1552 4.6 device id and revision id the memory location 8006h is where the device id and revision id are stored. the upper nine bits hold the device id. the lower five bits hold the revision id. see section 10.4 ?user id, device id and configuration word access? for more information on accessing these memory locations. development tools, such as device programmers and debuggers, may be used to read the device id and revision id. 4.7 register definitions: device register 4-3: devid: device id register rrrrrr dev<8:3> bit 13 bit 8 rrrrrrrr dev<2:0> rev<4:0> bit 7 bit 0 legend: r = readable bit ?1? = bit is set ?0? = bit is cleared bit 13-5 dev<8:0>: device id bits bit 4-0 rev<4:0>: revision id bits these bits are used to identify the revision (see table under dev<8:0> above). device devid<13:0> values dev<8:0> rev<4:0> PIC12LF1552 0010 1011 110 x xxxx
PIC12LF1552 ds41674b-page 40 preliminary ? 2013 microchip technology inc. notes:
? 2013 microchip technology inc. preliminary ds41674b-page 41 PIC12LF1552 5.0 oscillator module 5.1 overview the oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing perfor- mance and minimizing power consumption. figure 5-1 illustrates a block diagram of the oscillator module. clock sources can be supplied from external clock oscillators. in addition, the system clock source can be supplied from one of two internal oscillators and pll circuits, with a choice of speeds selectable via software. additional clock features include: ? selectable system clock source between external or internal sources via software. the oscillator module can be configured in one of the following clock modes. 1. ecl ? external clock low-power mode (0 mhz to 0.5 mhz) 2. ecm ? external clock medium-power mode (0.5 mhz to 4 mhz) 3. ech ? external clock high-power mode (4 mhz to 20 mhz) 4. intosc ? internal oscillator (31 khz to 32 mhz) clock source modes are selected by the fosc<1:0> bits in the configuration words. the fosc bits determine the type of oscillator that will be used when the device is first powered. the ec clock mode relies on an external logic level signal as the device clock source. the intosc internal oscillator block produces low and high frequency clock sources, designated lfintosc and hfintosc. (see internal oscillator block, figure 5-1 ). a wide selection of device clock frequencies may be derived from these clock sources. figure 5-1: simplified pic ? mcu clock source block diagram postscaler mux 16 mhz 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 250 khz 125 khz 62.5 khz 31.25 khz 31 khz 31 khz source wdt, pwrt and other modules mux sleep cpu and peripherals clock control scs<1:0> fosc<1:0> clkin ec intosc ircf<3:0> 16 mhz primary osc start-up control logic 4 22 4x pll
PIC12LF1552 ds41674b-page 42 preliminary ? 2013 microchip technology inc. 5.2 clock source types clock sources can be classified as external or internal. external clock sources rely on external circuitry for the clock source to function. examples are: oscillator modules (ec mode). internal clock sources are contained within the oscillator module. the oscillator block has two internal oscillators that are used to generate two system clock sources: the 16 mhz high-frequency internal oscillator (hfintosc) and the 31 khz low-frequency internal oscillator (lfintosc). the system clock can be selected between external or internal clock sources via the system clock select (scs) bits in the osccon register. see section 5.3 ?clock switching? for additional information. 5.2.1 external clock sources an external clock source can be used as the device system clock by performing one of the following actions: ? program the fosc<1:0> bits in the configuration words to select an external clock source that will be used as the default system clock upon a device reset. ? clear the scs<1:0> bits in the osccon register to switch the system clock source to: - an external clock source determined by the value of the fosc bits. see section 5.3 ?clock switching? for more informa- tion. 5.2.1.1 ec mode the external clock (ec) mode allows an externally generated logic level signal to be the system clock source. when operating in this mode, an external clock source is connected to the clkin input. clkout is available for general purpose i/o or clkout. figure 5-2 shows the pin connections for ec mode. ec mode has three power modes to select from through configuration words: ? high power, 4-20 mhz (fosc = 11 ) ? medium power, 0.5-4 mhz (fosc = 10 ) ? low power, 0-0.5 mhz (fosc = 01 ) when ec mode is selected, there is no delay in opera- tion after a power-on reset (por) or wake-up from sleep. because the pic ? mcu design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. upon restarting the external clock, the device will resume operation as if no time had elapsed. figure 5-2: external clock (ec) mode operation clkin clkout clock from ext. system pic ? mcu f osc /4 or i/o (1) note 1: output depends upon clkouten bit of the configuration words.
? 2013 microchip technology inc. preliminary ds41674b-page 43 PIC12LF1552 5.2.2 internal clock sources the device may be configured to use the internal oscil- lator block as the system clock by performing either of the following actions: ? program the fosc<1:0> bits in configuration words to select the intosc clock source, which will be used as the default system clock upon a device reset. ? set the scs<1:0> bits in the osccon register to ? 1x ? to switch the system clock source to the internal oscillator during run-time. see section 5.3 ?clock switching? for more information. in intosc mode, the clkin pin is available for general purpose i/o. the clkout pin is available for general purpose i/o or clkout. the function of the clkout pin is determined by the c lkouten bit in configuration words. the internal oscillator block has two independent oscillators. 1. the hfintosc (high-frequency internal oscillator) is factory calibrated and operates at 16 mhz. 2. the lfintosc (low-frequency internal oscillator) is uncalibrated and operates at 31 khz. 5.2.2.1 hfintosc the high-frequency internal oscillator (hfintosc) is a factory calibrated 16 mhz internal clock source. the outputs of the hfintosc connects to a prescaler and multiplexer (see figure 5-1 ). one of multiple frequencies derived from the hfintosc can be selected via software using the ircf<3:0> bits of the osccon register. see section 5.2.2.4 ?internal oscillator clock switch timing? for more information. the hfintosc is enabled by: ? configure the ircf<3:0> bits of the osccon register for the desired hf frequency, and ?fosc<1:0> = 00 , or ? set the system clock source (scs) bits of the osccon register to ? 1x ?. a fast start-up oscillator allows internal circuits to power-up and stabilize before switching to hfintosc. the high-frequency internal oscillator ready bit (hfiofr) of the oscstat register indicates when the hfintosc is running. the high-frequency internal oscillator stable bit (hfiofs) of the oscstat register indicates when the hfintosc is running within 0.5% of its final value. 5.2.2.2 lfintosc the low-frequency internal oscillator (lfintosc) is an uncalibrated 31 khz internal clock source. the output of the lfintosc connects to a multiplexer (see figure 5-1 ). select 31 khz, via software, using the ircf<3:0> bits of the osccon register. see section 5.2.2.4 ?internal oscillator clock switch timing? for more information. the lfintosc is also the source for the power-up timer (pwrt) and watchdog timer (wdt). the lfintosc is enabled by selecting 31 khz (ircf<3:0> bits of the osccon register = 000x) as the system clock source (scs bits of the osccon register = 1x ), or when any of the following are enabled: ? configure the ircf<3:0> bits of the osccon register for the lf frequency, and ?fosc<1:0> = 00 , or ? set the system clock source (scs) bits of the osccon register to ? 1x ? peripherals that use the lfintosc are: ? power-up timer (pwrt) ? watchdog timer (wdt) the low-frequency internal oscillator ready bit (lfiofr) of the oscstat register indicates when the lfintosc is running.
PIC12LF1552 ds41674b-page 44 preliminary ? 2013 microchip technology inc. 5.2.2.3 internal oscillator frequency selection the system clock speed can be selected via software using the internal oscillator frequency select bits ircf<3:0> of the osccon register. the outputs of the 16 mhz hfintosc postscaler and the lfintosc connect to a multiplexer (see figure 5-1 ). the internal oscillator frequency select bits ircf<3:0> of the osccon register select the frequency. one of the following frequencies can be selected via software: - 32 mhz (requires 4x pll) -16 mhz -8 mhz -4 mhz -2 mhz -1 mhz - 500 khz (default after reset) - 250 khz - 125 khz - 62.5 khz - 31.25 khz - 31 khz (lfintosc) the ircf<3:0> bits of the osccon register allow duplicate selections for some frequencies. these dupli- cate choices can offer system design trade-offs. lower power consumption can be obtained when changing oscillator sources for a given frequency. faster transi- tion times can be obtained between frequency changes that use the same oscillator source. 5.2.2.4 internal oscillator clock switch timing when switching between the hfintosc and the lfintosc, the new oscillator may already be shut down to save power (see figure 5-3 ). if this is the case, there is a delay after the ircf<3:0> bits of the osccon register are modified before the frequency selection takes place. the oscstat register will reflect the current active status of the hfintosc and lfintosc oscillators. the sequence of a frequency selection is as follows: 1. ircf<3:0> bits of the osccon register are modified. 2. if the new clock is shut down, a clock start-up delay is started. 3. clock switch circuitry waits for a falling edge of the current clock. 4. clock switch is complete. see figure 5-3 for more details. if the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. start-up delay specifications are located in the oscillator tables of section 21.0 ?electrical specifications? . 5.2.2.5 32 mhz internal oscillator frequency selection the internal oscillator block can be used with the 4x pll to produce a 32 mhz internal system clock source. the following settings are required to use the 32 mhz internal clock source: ? the fosc bits in configuration word 1 must be set to use the intosc source as the device system clock (fosc<1:0> = 00 ). ? the scs bits in the osccon register must be cleared to use the clock determined by fosc<1:0> in configuration word 1 (scs<1:0> = 00 ). ? the ircf bits in the osccon register must be set to the 8 mhz hfintosc set to use (ircf<3:0> = 1110 ). ? the spllen bit in the osccon register must be set to enable the 4x pll. the 4x pll is not available for use with the internal oscillator when the scs bits of the osccon register are set to ? 1x ?. the scs bits must be set to ? 00 ? to use the 4x pll with the internal oscillator. note: following any reset, the ircf<3:0> bits of the osccon register are set to ? 0111 ? and the frequency selection is set to 500 khz. the user can modify the ircf bits to select a different frequency.
? 2013 microchip technology inc. preliminary ds41674b-page 45 PIC12LF1552 figure 5-3: internal oscillator switch timing hfintosc lfintosc ircf <3:0> system clock hfintosc lfintosc ircf <3:0> system clock ?? 0 ?? 0 ?? 0 ?? 0 start-up time 2-cycle sync running 2-cycle sync running hfintosc lfintosc (wdt disabled) hfintosc lfintosc (wdt enabled) lfintosc hfintosc ircf <3:0> system clock = 0 ? 0 start-up time 2-cycle sync running lfintosc hfintosc lfintosc turns off unless wdt is enabled
PIC12LF1552 ds41674b-page 46 preliminary ? 2013 microchip technology inc. 5.3 clock switching the system clock source can be switched between external and internal clock sources via software using the system clock select (scs) bits of the osccon register. the following clock sources can be selected using the scs bits: ? default system oscillator determined by fosc bits in configuration words ? internal oscillator block (intosc) 5.3.1 system clock select (scs) bits the system clock select (scs) bits of the osccon register selects the system clock source that is used for the cpu and peripherals. ? when the scs bits of the osccon register = 00 , the system clock source is determined by value of the fosc<1:0> bits in the configuration words. ? when the scs bits of the osccon register = 1x , the system clock source is chosen by the internal oscillator frequency selected by the ircf<3:0> bits of the osccon register. after a reset, the scs bits of the osccon register are always cleared. when switching between clock sources, a delay is required to allow the new clock to stabilize. these oscillator delays are shown in table 5-2 . table 5-1: oscillator switching delays switch from switch to frequency oscillator delay sleep/por lfintosc hfintosc 31 khz 31.25khz-32mhz 2 cycles ec dc ? 20 mhz lfintosc ec dc ? 20 mhz 1 cycle of each any clock source hfintosc 31.25 khz-16 mhz 2 ? s (approx.) any clock source lfintosc 31 khz 1 cycle of each
? 2013 microchip technology inc. preliminary ds41674b-page 47 PIC12LF1552 5.4 register definitions: oscillator control register 5-1: osccon: os cillator control register r/w-0/0 r/w-0/0 r/w-1/1 r/w-1/1 r/w-1/1 u-0 r/w-0/0 r/w-0/0 spllen ircf<3:0> ? scs<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 spllen: software pll enable bit 1 = 4x pll is enabled 0 = 4x pll is disabled bit 6-3 ircf<3:0>: internal oscillator frequency select bits 1111 =16mhz 1110 =8mhz 1101 =4mhz 1100 =2mhz 1011 =1mhz 1010 =500khz (1) 1001 =250khz (1) 1000 =125khz (1) 0111 = 500 khz (default upon reset) 0110 =250khz 0101 =125khz 0100 =62.5khz 001x =31.25khz 000x = 31 khz (lfintosc) bit 2 unimplemented: read as ? 0 ? bit 1-0 scs<1:0>: system clock select bits 1x = internal oscillator block 01 = reserved 00 = clock determined by fosc<1:0> in configuration words note 1: duplicate frequency derived from hfintosc.
PIC12LF1552 ds41674b-page 48 preliminary ? 2013 microchip technology inc. table 5-2: summary of registers asso ciated with clock sources table 5-3: summary of configuration word wi th clock sources register 5-2: oscstat: oscillator status register u-0 r-0/q u-0 r-0/q u-0 u-0 r-0/q r-0/q ? pllr ? hfiofr ? ? lfiofr hfiofs bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = conditional bit 7 unimplemented: read as ? 0 ? bit 6 pllr 4x pll ready bit 1 = 4x pll is ready 0 = 4x pll is not ready bit 5 unimplemented: read as ? 0 ? bit 4 hfiofr: high-frequency internal oscillator ready bit 1 = 16 mhz internal oscillator (hfintosc) is ready 0 = 16 mhz internal oscillator (hfintosc) is not ready bit 3-2 unimplemented: read as ? 0 ? bit 1 lfiofr: low-frequency internal oscillator ready bit 1 = 31 khz internal oscillator (lfintosc) is ready 0 = 31 khz internal oscillator (lfintosc) is not ready bit 0 hfiofs: high-frequency internal oscillator stable bit 1 = 16 mhz internal oscillator (hfintosc) is stable 0 = 16 mhz internal oscillator (hfintosc) is not yet stable name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page osccon spllen ircf<3:0> ?scs<1:0> 47 oscstat ? pllr ?hfiofr ? ? lfiofr hfiofs 48 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by clock sources. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? ? ?clkouten boren<1:0> ? 36 7:0 cp mclre pwrte wdte<1:0> ? fosc<1:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by clock sources.
? 2013 microchip technology inc. preliminary ds41674b-page 49 PIC12LF1552 6.0 resets there are multiple ways to reset this device: ? power-on reset (por) ? brown-out reset (bor) ? low-power brown-out reset (lpbor) ?mclr reset ?wdt reset ? reset instruction ? stack overflow ? stack underflow ? programming mode exit to allow v dd to stabilize, an optional power-up timer can be enabled to extend the reset time after a bor or por event. a simplified block diagram of the on-chip reset circuit is shown in figure 6-1 . figure 6-1: simplified block di agram of on-chip reset circuit note 1: see table 6-1 for bor active conditions. device reset power-on reset wdt time-out brown-out reset lpbor reset reset instruction mclre sleep bor active (1) pwrt r done pwrte lfintosc v dd icsp? programming mode exit stack pointer mclr
PIC12LF1552 ds41674b-page 50 preliminary ? 2013 microchip technology inc. 6.1 power-on reset (por) the por circuit holds the device in reset until v dd has reached an acceptable level for minimum operation. slow rising v dd , fast operating speeds or analog performance may require greater than minimum v dd . the pwrt, bor or mclr features can be used to extend the start-up period until all device operation conditions have been met. 6.1.1 power-up timer (pwrt) the power-up timer provides a nominal 64 ms time-out on por or brown-out reset. the device is held in reset as long as pwrt is active. the pwrt delay allows additional time for the v dd to rise to an acceptable level. the power-up timer is enabled by clearing the pwrte bit in configuration words. the power-up timer starts after the release of the por and bor. for additional information, refer to application note an607, ?power-up trouble shooting? (ds00607). 6.2 brown-out reset (bor) the bor circuit holds the device in reset when v dd reaches a selectable minimum level. between the por and bor, complete voltage range coverage for execution protection can be implemented. the brown-out reset module has four operating modes controlled by the boren<1:0> bits in configu- ration words. the four operating modes are: ? bor is always on ? bor is off when in sleep ? bor is controlled by software ? bor is always off refer to tab le 6 - 1 for more information. the brown-out reset voltage level is selectable by configuring the borv bit in configuration words. a v dd noise rejection filter prevents the bor from triggering on small events. if v dd falls below v bor for a duration greater than parameter t bordc , the device will reset. see figure 6-2 for more information. table 6-1: bor operating modes 6.2.1 bor is always on when the boren bits of configuration words are pro- grammed to ? 11 ?, the bor is always on. the device start-up will be delayed until the bor is ready and v dd is higher than the bor threshold. bor protection is active during sleep. the bor does not delay wake-up from sleep. 6.2.2 bor is off in sleep when the boren bits of configuration words are pro- grammed to ? 10 ?, the bor is on, except in sleep. the device start-up will be delayed until the bor is ready and v dd is higher than the bor threshold. bor protection is not active during sleep. the device wake-up will be delayed until the bor is ready. 6.2.3 bor controlled by software when the boren bits of configuration words are programmed to ? 01 ?, the bor is controlled by the sboren bit of the borcon register. the device start-up is not delayed by the bor ready condition or the v dd level. bor protection begins as soon as the bor circuit is ready. the status of the bor circuit is reflected in the borrdy bit of the borcon register. bor protection is unchanged by sleep. boren<1:0> sboren device mode bor mode instruction execution upon: release of por or wake-up from sleep 11 x x active waits for bor ready (1) (borrdy = 1 ) 10 x awake active waits for bor ready (borrdy = 1 ) sleep disabled 01 1 x active waits for bor ready (1) (borrdy = 1 ) 0 x disabled begins immediately (borrdy = x) 00 x xdisabled note 1: in these specific cases, ?release of por? and ?wake-up from sleep,? there is no delay in start-up. the bor ready flag, (borrdy = 1 ), will be set before the cpu is ready to execute instructions because the bor circuit is forced on by the boren<1:0> bits.
? 2013 microchip technology inc. preliminary ds41674b-page 51 PIC12LF1552 figure 6-2: brown -out situations 6.3 register definitions: bor control register 6-1: borco n: brown-out reset control register r/w-1/u r/w-0/u u-0 u-0 u-0 u-0 u-0 r-q/u sboren borfs ? ? ? ? ? borrdy bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 sboren: software brown-out reset enable bit if boren <1:0> in configuration word s = 01 : 1 = bor enabled 0 = bor disabled if boren <1:0> in configuration word s ? 00 : sboren is read/write, but has no effect on the bor. bit 6 borfs: brown-out reset fast start bit (1) if boren <1:0> = 10 (disabled in sleep) or boren<1:0> = 01 (under software control): 1 = band gap is forced on always (covers sleep/wake-up/operating cases) 0 = band gap operates normally, and may turn off if boren<1:0> = 11 (always on) or boren<1:0> = 00 (always off) borfs is read/write, but has no effect. bit 5-1 unimplemented: read as ? 0 ? bit 0 borrdy: brown-out reset circuit ready status bit 1 = the brown-out reset circuit is active 0 = the brown-out reset circuit is inactive note 1: boren<1:0> bits are located in configuration words. t pwrt (1) v bor v dd internal reset v bor v dd internal reset t pwrt (1) < t pwrt t pwrt (1) v bor v dd internal reset note 1: t pwrt delay only if pwrte bit is programmed to ? 0 ?.
PIC12LF1552 ds41674b-page 52 preliminary ? 2013 microchip technology inc. 6.4 low-power brown-out reset (lpbor) the low-power brown-out reset (lpbor) is an essential part of the reset subsystem. refer to figure 6-1 to see how the bor interacts with other modules. the lpbor is used to monitor the external v dd pin. when too low of a voltage is detected, the device is held in reset. when this occurs, a register bit (bor ) is changed to indicate that a bor reset has occurred. the same bit is set for both the bor and the lpbor. refer to register 6-2 . 6.4.1 enabling lpbor the lpbor is controlled by the lpbor bit of configuration words. when the device is erased, the lpbor module defaults to disabled. 6.4.1.1 lpbor module output the output of the lpbor module is a signal indicating whether or not a reset is to be asserted. this signal is or?d together with the reset signal of the bor module to provide the generic bor signal which goes to the pcon register and to the power control block. 6.5 mclr the mclr is an optional external input that can reset the device. the mclr function is controlled by the mclre bit of configuration words and the lvp bit of configuration words ( table 6-2 ). 6.5.1 mclr enabled when mclr is enabled and the pin is held low, the device is held in reset. the mclr pin is connected to v dd through an internal weak pull-up. the device has a noise filter in the mclr reset path. the filter will detect and ignore small pulses. 6.5.2 mclr disabled when mclr is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. see section 11.3 ?porta regis- ters? for more information. 6.6 watchdog timer (wdt) reset the watchdog timer generates a reset if the firmware does not issue a clrwdt instruction within the time-out period. the to and pd bits in the status register are changed to indicate the wdt reset. see section 9.0 ?watchdog timer (wdt)? for more information. 6.7 reset instruction a reset instruction will cause a device reset. the ri bit in the pcon register will be set to ? 0 ?. see ta b l e 6 - 4 for default conditions after a reset instruction has occurred. 6.8 stack overflow/underflow reset the device can reset when the stack overflows or underflows. the stkovf or stkunf bits of the pcon register indicate the reset condition. these resets are enabled by setting the stvren bit in configuration words. see section 3.5.2 ?overflow/underflow reset? for more information. 6.9 programming mode exit upon exit of programming mode, the device will behave as if a por had just occurred. 6.10 power-up timer the power-up timer optionally delays device execution after a bor or por event. this timer is typically used to allow v dd to stabilize before allowing the device to start running. the power-up timer is controlled by the pwrte bit of configuration words. 6.11 start-up sequence upon the release of a por or bor, the following must occur before the device will begin executing: 1. power-up timer runs to completion (if enabled). 2. mclr must be released (if enabled). the total time-out will vary based on oscillator configu- ration and power-up timer configuration. see section 5.0 ?oscillator module? for more informa- tion. the power-up timer runs independently of mclr reset. if mclr is kept low long enough, the power-up timer will expire. upon bringing mclr high, the device will begin execution immediately (see figure 6-3 ). this is useful for testing purposes or to synchronize more than one device operating in parallel. table 6-2: mclr configuration mclre lvp mclr 00 disabled 10 enabled x1 enabled note: a reset does not drive the mclr pin low.
? 2013 microchip technology inc. preliminary ds41674b-page 53 PIC12LF1552 figure 6-3: reset start-up sequence t mclr t pwrt v dd internal por power-up timer mclr internal reset internal oscillator oscillator f osc external clock (ec) clkin f osc
PIC12LF1552 ds41674b-page 54 preliminary ? 2013 microchip technology inc. 6.12 determining the cause of a reset upon any reset, multiple bits in the status and pcon registers are updated to indicate the cause of the reset. ta b l e 6 - 3 and tab le 6 - 4 show the reset conditions of these registers. table 6-3: reset status bits and their significance table 6-4: reset condition for special registers stkovf stkunf rwdt rmclr ri por bor to pd condition 0 0 1 1 10 x11 power-on reset 0 0 1 1 10 x0x illegal, to is set on por 0 0 1 1 10 xx0 illegal, pd is set on por 0 0 u 1 1u 011 brown-out reset u u 0 u uu u0u wdt reset u u u u uu u00 wdt wake-up from sleep u u u u uu u10 interrupt wake-up from sleep u u u 0 uu uuu mclr reset during normal operation u u u 0 uu u10 mclr reset during sleep u u u u 0 u u u u reset instruction executed 1 u u u uu uuu stack overflow reset (stvren = 1 ) u 1 u u uu uuu stack underflow reset (stvren = 1 ) condition program counter status register pcon register power-on reset 0000h ---1 1000 00-- 110x mclr reset during normal operation 0000h ---u uuuu uu-- 0uuu mclr reset during sleep 0000h ---1 0uuu uu-- 0uuu wdt reset 0000h ---0 uuuu uu-- uuuu wdt wake-up from sleep pc + 1 ---0 0uuu uu-- uuuu brown-out reset 0000h ---1 1uuu 00-- 11u0 interrupt wake-up from sleep pc + 1 (1) ---1 0uuu uu-- uuuu reset instruction executed 0000h ---u uuuu uu-- u0uu stack overflow reset (stvren = 1 ) 0000h ---u uuuu 1u-- uuuu stack underflow reset (stvren = 1 ) 0000h ---u uuuu u1-- uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ? 0 ?. note 1: when the wake-up is due to an interrupt and the global interrupt enable bit (gie) is set, the return address is pushed on the stack and pc is loaded with the interrupt vector (0004h) after execution of pc + 1.
? 2013 microchip technology inc. preliminary ds41674b-page 55 PIC12LF1552 6.13 power control (pcon) register the power control (pcon) register contains flag bits to differentiate between a: ? power-on reset (por ) ? brown-out reset (bor ) ? reset instruction reset (ri ) ?mclr reset (rmclr ) ? watchdog timer reset (rwdt ) ? stack underflow reset (stkunf) ? stack overflow reset (stkovf) the pcon register bits are shown in register 6-2 . 6.14 register definitions: power control register 6-2: pcon: power control register r/w/hs-0/q r/w/hs-0/q u-0 r/w/hc-1/q r/w/ hc-1/q r/w/hc-1/q r/w/hc-q/u r/w/hc-q/u stkovf stkunf ? rwdt rmclr ri por bor bit 7 bit 0 legend: hc = bit is cleared by hardware hs = bit is set by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 stkovf: stack overflow flag bit 1 = a stack overflow occurred 0 = a stack overflow has not occurred or cleared by firmware bit 6 stkunf: stack underflow flag bit 1 = a stack underflow occurred 0 = a stack underflow has not occurred or cleared by firmware bit 5 unimplemented: read as ? 0 ? bit 4 rwdt : watchdog timer reset flag bit 1 = a watchdog timer reset has not occurred or set by firmware 0 = a watchdog timer reset has occurred (cleared by hardware) bit 3 rmclr : mclr reset flag bit 1 = a mclr reset has not occurred or set by firmware 0 = a mclr reset has occurred (cleared by hardware) bit 2 ri : reset instruction flag bit 1 = a reset instruction has not been executed or set by firmware 0 = a reset instruction has been executed (cleared by hardware) bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a power-on reset or brown-out reset occurs)
PIC12LF1552 ds41674b-page 56 preliminary ? 2013 microchip technology inc. table 6-5: summary of registers associated with resets table 6-6: summary of config uration word with resets name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page borcon sboren borfs ? ? ? ? ? borrdy 51 pcon stkovf stkunf ?rwdt rmclr ri por bor 55 status ? ? ?to pd z dc c 16 wdtcon ? ? wdtps<4:0> swdten 73 legend: ? = unimplemented bit, reads as ? 0 ?. shaded cells are not used by resets. note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? ? ? clkouten boren<1:0> ? 36 7:0 cp mclre pwrte wdte<1:0> ? fosc<1:0> config2 13:8 ? ? lvp ? lpbor borv stvren ? 37 7:0 ? ? ? ? ? ? wrt<1:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by resets.
? 2013 microchip technology inc. preliminary ds41674b-page 57 PIC12LF1552 7.0 interrupts the interrupt feature allows certain events to preempt normal program flow. firmware is used to determine the source of the interrupt and act accordingly. some interrupts can be configured to wake the mcu from sleep mode. this chapter contains the following information for interrupts: ? operation ? interrupt latency ? interrupts during sleep ?int pin ? automatic context saving many peripherals produce interrupts. refer to the corresponding chapters for details. a block diagram of the interrupt logic is shown in figure 7-1 . figure 7-1: interrupt logic tmr0if tmr0ie intf inte iocif iocie interrupt to cpu wake-up (if in sleep mode) gie adif bclif bclie peie peripheral interrupts adie
PIC12LF1552 ds41674b-page 58 preliminary ? 2013 microchip technology inc. 7.1 operation interrupts are disabled upon any device reset. they are enabled by setting the following bits: ? gie bit of the intcon register ? interrupt enable bit(s) for the specific interrupt event(s) ? peie bit of the intcon register (if the interrupt enable bit of the interrupt event is contained in the pie1 and pie2 registers) the intcon, pir1, and pir2 registers record individ- ual interrupts via interrupt flag bits. interrupt flag bits will be set, regardless of the status of the gie, peie and individual interrupt enable bits. the following events happen when an interrupt event occurs while the gie bit is set: ? current prefetched instruction is flushed ? gie bit is cleared ? current program counter (pc) is pushed onto the stack ? critical registers are automatically saved to the shadow registers (see ? section 7.5 ?automatic context saving? .? ) ? pc is loaded with the interrupt vector 0004h the firmware within the interrupt service routine (isr) should determine the source of the interrupt by polling the interrupt flag bits. the interrupt flag bits must be cleared before exiting the isr to avoid repeated interrupts. because the gie bit is cleared, any interrupt that occurs while executing the isr will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. the retfie instruction exits the isr by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the gie bit. for additional information on a specific interrupt?s operation, refer to its peripheral chapter. 7.2 interrupt latency interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. the latency for synchronous interrupts is three or four instruction cycles. for asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. see figure 7-2 and figure 7.3 for more details. note 1: individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: all interrupts will be ignored while the gie bit is cleared. any interrupt occurring while the gie bit is clear will be serviced when the gie bit is set again.
? 2013 microchip technology inc. preliminary ds41674b-page 59 PIC12LF1552 figure 7-2: interrupt latency q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 fosc clkr pc 0004h 0005h pc inst(0004h) nop gie q1 q2 q3 q4 q1 q2 q3 q4 1 cycle instruction at pc pc inst(0004h) nop 2 cycle instruction at pc fsr addr pc+1 pc+2 0004h 0005h pc inst(0004h) nop gie pc pc-1 3 cycle instruction at pc execute interrupt inst(pc) interrupt sampled during q1 inst(pc) pc-1 pc+1 nop pc new pc/ pc+1 0005h pc-1 pc+1/fsr addr 0004h nop interrupt gie interrupt inst(pc) nop nop fsr addr pc+1 pc+2 0004h 0005h pc inst(0004h) nop gie pc pc-1 3 cycle instruction at pc interrupt inst(pc) nop nop nop inst(0005h) execute execute execute
PIC12LF1552 ds41674b-page 60 preliminary ? 2013 microchip technology inc. figure 7-3: int pin interrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 f osc clkout int pin intf gie instruction flow pc instruction fetched instruction executed interrupt latency pc pc + 1 pc + 1 0004h 0005h inst (0004h) inst (0005h) forced nop inst (pc) inst (pc + 1) inst (pc ? 1) inst (0004h) forced nop inst (pc) ? note 1: intf flag is sampled here (every q1). 2: asynchronous interrupt latency = 3-5 t cy . synchronous latency = 3-4 t cy , where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: for minimum width of int pulse, refer to ac specifications in section 21.0 ?electrical specifications? ? . 4: intf is enabled to be set any time during the q4-q1 cycles. (1) (2) (3) (4) (1)
? 2013 microchip technology inc. preliminary ds41674b-page 61 PIC12LF1552 7.3 interrupts during sleep some interrupts can be used to wake from sleep. to wake from sleep, the peripheral must be able to operate without the system clock. the interrupt source must have the appropriate interrupt enable bit(s) set prior to entering sleep. on waking from sleep, if the gie bit is also set, the processor will branch to the interrupt vector. otherwise, the processor will continue executing instructions after the sleep instruction. the instruction directly after the sleep instruction will always be executed before branching to the isr. refer to section 8.0 ?power-down mode (sleep)? for more details. 7.4 int pin the int pin can be used to generate an asynchronous edge-triggered interrupt. this interrupt is enabled by setting the inte bit of the intcon register. the intedg bit of the option_reg register determines on which edge the interrupt will occur. when the intedg bit is set, the rising edge will cause the interrupt. when the intedg bit is clear, the falling edge will cause the interrupt. the intf bit of the intcon register will be set when a valid edge appears on the int pin. if the gie and inte bits are also set, the processor will redirect program execution to the interrupt vector. 7.5 automatic context saving upon entering an interrupt, the return pc address is saved on the stack. additionally, the following registers are automatically saved in the shadow registers: ? w register ? status register (except for to and pd ) ? bsr register ? fsr registers ? pclath register upon exiting the interrupt service routine, these regis- ters are automatically restored. any modifications to these registers during the isr will be lost. if modifica- tions to any of these registers are desired, the corre- sponding shadow register should be modified and the value will be restored when exiting the isr. the shadow registers are available in bank 31 and are readable and writable. depending on the user?s appli- cation, other registers may also need to be saved.
PIC12LF1552 ds41674b-page 62 preliminary ? 2013 microchip technology inc. 7.6 register definitions: interrupt control register 7-1: intcon: interrupt control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-0/0 gie peie tmr0ie inte iocie tmr0if intf iocif (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 gie: global interrupt enable bit 1 = enables all active interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all active peripheral interrupts 0 = disables all peripheral interrupts bit 5 tmr0ie: timer0 overflow interrupt enable bit 1 = enables the timer0 interrupt 0 = disables the timer0 interrupt bit 4 inte: int external interrupt enable bit 1 = enables the int external interrupt 0 = disables the int external interrupt bit 3 iocie: interrupt-on-change enable bit 1 = enables the interrupt-on-change 0 = disables the interrupt-on-change bit 2 tmr0if: timer0 overflow interrupt flag bit 1 = tmr0 register has overflowed 0 = tmr0 register did not overflow bit 1 intf: int external interrupt flag bit 1 = the int external interrupt occurred 0 = the int external interrupt did not occur bit 0 iocif: interrupt-on-change interrupt flag bit (1) 1 = when at least one of the interrupt-on-change pins changed state 0 = none of the interrupt-on-change pins have changed state note 1: the iocif flag bit is read-only and cleared when all the interrupt-on-change flags in the iocbf register have been cleared by software. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
? 2013 microchip technology inc. preliminary ds41674b-page 63 PIC12LF1552 register 7-2: pie1: peripheral interrupt enable register 1 u-0 r/w-0/0 u-0 u-0 r/w-0/0 u-0 u-0 u-0 ?adie ? ? sspie ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6 adie: analog-to-digital converter (adc) interrupt enable bit 1 = enables the adc interrupt 0 = disables the adc interrupt bit 5-4 unimplemented: read as ? 0 ? bit 3 sspie: synchronous serial port (mssp) interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 2-0 unimplemented: read as ? 0 ? note: bit peie of the intcon register must be set to enable any peripheral interrupt.
PIC12LF1552 ds41674b-page 64 preliminary ? 2013 microchip technology inc. register 7-3: pie2: peripheral interrupt enable register 2 u-0 u-0 u-0 u-0 r/w-0/0 u-0 u-0 u-0 ? ? ? ?bclie ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented: read as ? 0 ? bit 3 bclie: mssp bus collision interrupt enable bit 1 = enables the mssp bus collision interrupt 0 = disables the mssp bus collision interrupt bit 2-0 unimplemented: read as ? 0 ? note: bit peie of the intcon register must be set to enable any peripheral interrupt.
? 2013 microchip technology inc. preliminary ds41674b-page 65 PIC12LF1552 register 7-4: pir1: peripheral interrupt request register 1 u-0 r/w-0/0 u-0 u-0 r/w-0/0 u-0 u-0 u-0 ?adif ? ? sspif ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6 adif: adc interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 5-4 unimplemented: read as ? 0 ? bit 3 sspif: synchronous serial port (mssp) interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 2-0 unimplemented: read as ? 0 ? note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC12LF1552 ds41674b-page 66 preliminary ? 2013 microchip technology inc. register 7-5: pir2: peripheral interrupt request register 2 u-0 u-0 u-0 u-0 r/w-0/0 u-0 u-0 u-0 ? ? ? ?bclif ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented: read as ? 0 ? bit 3 bclif: mssp bus collision interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 2-0 unimplemented: read as ? 0 ? note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
? 2013 microchip technology inc. preliminary ds41674b-page 67 PIC12LF1552 table 7-1: summary of registers associated with interrupts name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 62 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 140 pie1 ?adie ? ? sspie ? ? ? 63 pie2 ? ? ? ?bclie ? ? ? 64 pir1 ?adif ? ? sspif ? ? ? 65 pir2 ? ? ? ?bclif ? ? ? 66 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by interrupts.
PIC12LF1552 ds41674b-page 68 preliminary ? 2013 microchip technology inc. notes:
? 2013 microchip technology inc. preliminary ds41674b-page 69 PIC12LF1552 8.0 power-down mode (sleep) the power-down mode is entered by executing a sleep instruction. upon entering sleep mode, the following conditions exist: 1. wdt will be cleared but keeps running, if enabled for operation during sleep. 2. pd bit of the status register is cleared. 3. to bit of the status register is set. 4. cpu clock is disabled. 5. 31 khz lfintosc is unaffected and peripherals that operate from it may continue operation in sleep. 6. adc is unaffected, if the dedicated frc clock is selected. 7. i/o ports maintain the status they had before sleep was executed (driving high, low or high-impedance). 8. resets other than wdt are not affected by sleep mode. refer to individual chapters for more details on peripheral operation during sleep. to minimize current consumption, the following condi- tions should be considered: ? i/o pins should not be floating ? external circuitry sinking current from i/o pins ? internal circuitry sourcing current from i/o pins ? current draw from pins with internal weak pull-ups ? modules using 31 khz lfintosc i/o pins that are high-impedance inputs should be pulled to v dd or v ss externally to avoid switching currents caused by floating inputs. examples of internal circuitry that might be sourcing current include the fvr module. see section 13.0 ?fixed voltage reference (fvr)? for more information on this module. 8.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin, if enabled 2. bor reset, if enabled 3. por reset 4. watchdog timer, if enabled 5. any external interrupt 6. interrupts by peripherals capable of running dur- ing sleep (see individual peripheral for more information) the first three events will cause a device reset. the last three events are considered a continuation of pro- gram execution. to determine whether a device reset or wake-up event occurred, refer to section 6.12 ?determining the cause of a reset? . when the sleep instruction is being executed, the next instruction (pc + 1) is prefetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. wake-up will occur regardless of the state of the gie bit. if the gie bit is disabled, the device continues execution at the instruction after the sleep instruction. if the gie bit is enabled, the device executes the instruction after the sleep instruction, the device will then call the interrupt service routine. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. the wdt is cleared when the device wakes up from sleep, regardless of the source of wake-up.
PIC12LF1552 ds41674b-page 70 preliminary ? 2013 microchip technology inc. 8.1.1 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction - sleep instruction will execute as a nop . - wdt and wdt prescaler will not be cleared -to bit of the status register will not be set -pd bit of the status register will not be cleared. ? if the interrupt occurs during or after the execu- tion of a sleep instruction - sleep instruction will be completely executed - device will immediately wake-up from sleep - wdt and wdt prescaler will be cleared -to bit of the status register will be set -pd bit of the status register will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . figure 8-1: wake-up from sleep through interrupt table 8-1: summary of registers as sociated with power-down mode q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 clkin (1) clkout (2) interrupt flag gie bit (intcon reg.) instruction flow pc instruction fetched instruction executed pc pc + 1 pc + 2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (4) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) forced nop pc + 2 0004h 0005h forced nop t ost (3) pc + 2 note 1: external clock. high, medium, low mode assumed. 2: clkout is not available in xt, hs, or lp oscillator modes, but shown here for timing reference. 3: t ost = 1024 t osc (drawing not to scale). this delay applies only to xt, hs or lp oscillator modes. 4: gie = 1 assumed. in this case after wake-up, the processor calls the isr at 0004h. if gie = 0 , execution will continue in-line. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 62 iocaf ? ? iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 99 iocan ? ? iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 99 iocap ? ? iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 99 pie1 ?adie ? ? sspie ? ? ? 63 pie2 ? ? ? ?bclie ? ? ? 64 pir1 ?adif ? ? sspif ? ? ? 65 pir2 ? ? ? ?bclif ? ? ? 66 status ? ? ?to pd z dc c 16 wdtcon ? ? wdtps<4:0> swdten 73 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used in power-down mode.
? 2013 microchip technology inc. preliminary ds41674b-page 71 PIC12LF1552 9.0 watchdog timer (wdt) the watchdog timer is a system timer that generates a reset if the firmware does not issue a clrwdt instruction within the time-out period. the watchdog timer is typically used to recover the system from unexpected events. the wdt has the following features: ? independent clock source ? multiple operating modes - wdt is always on - wdt is off when in sleep - wdt is controlled by software - wdt is always off ? configurable time-out period is from 1 ms to 256 seconds (nominal) ? multiple reset conditions ? operation during sleep figure 9-1: watchdog ti mer block diagram lfintosc 23-bit programmable prescaler wdt wdt time-out wdtps<4:0> swdten sleep wdte<1:0> = 11 wdte<1:0> = 01 wdte<1:0> = 10
PIC12LF1552 ds41674b-page 72 preliminary ? 2013 microchip technology inc. 9.1 independent clock source the wdt derives its time base from the 31 khz lfintosc internal oscillator. time intervals in this chapter are based on a nominal interval of 1 ms. see section 21.0 ?electrical specifications? for the lfintosc tolerances. 9.2 wdt operating modes the watchdog timer module has four operating modes controlled by the wdte<1:0> bits in configuration words. see ta b l e 9 - 1 . 9.2.1 wdt is always on when the wdte bits of configuration words are set to ? 11 ?, the wdt is always on. wdt protection is active during sleep. 9.2.2 wdt is off in sleep when the wdte bits of configuration words are set to ? 10 ?, the wdt is on, except in sleep. wdt protection is not active during sleep. 9.2.3 wdt controlled by software when the wdte bits of configuration words are set to ? 01 ?, the wdt is controlled by the swdten bit of the wdtcon register. wdt protection is unchanged by sleep. see table 9-1 for more details. table 9-1: wdt operating modes 9.3 time-out period the wdtps bits of the wdtcon register set the time-out period from 1 ms to 256 seconds (nominal). after a reset, the default time-out period is two seconds. 9.4 clearing the wdt the wdt is cleared when any of the following conditions occur: ?any reset ? clrwdt instruction is executed ? device enters sleep ? device wakes up from sleep ? oscillator fail ? wdt is disabled see table 9-2 for more information. 9.5 operation during sleep when the device enters sleep, the wdt is cleared. if the wdt is enabled during sleep, the wdt resumes counting. when the device exits sleep, the wdt is cleared again. when a wdt time-out occurs while the device is in sleep, no reset is generated. instead, the device wakes up and resumes operation. the to and pd bits in the status register are changed to indicate the event. the rwdt bit in the pcon register can also be used. see section 3.0 ?memory organization? for more information. wdte<1:0> swdten device mode wdt mode 11 x xactive 10 x awake active sleep disabled 01 1 xactive 0 x disabled 00 x x disabled table 9-2: wdt clearing conditions conditions wdt wdte<1:0> = 00 cleared wdte<1:0> = 01 and swdten = 0 wdte<1:0> = 10 and enter sleep clrwdt command oscillator fail detected exit sleep + system clock = intosc, extclk change intosc divider (ircf bits) unaffected
? 2013 microchip technology inc. preliminary ds41674b-page 73 PIC12LF1552 9.6 register definitions: watchdog control register 9-1: wdtcon: wat chdog timer control register u-0 u-0 r/w-0/0 r/w-1/1 r/w-0/0 r/w-1/1 r/w-1/1 r/w-0/0 ? ? wdtps<4:0> swdten bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-1 wdtps<4:0>: watchdog timer period select bits (1) bit value = prescale rate 11111 = reserved. results in minimum interval (1:32) ? ? ? 10011 = reserved. results in minimum interval (1:32) 10010 = 1:8388608 (2 23 ) (interval 256s nominal) 10001 = 1:4194304 (2 22 ) (interval 128s nominal) 10000 = 1:2097152 (2 21 ) (interval 64s nominal) 01111 = 1:1048576 (2 20 ) (interval 32s nominal) 01110 = 1:524288 (2 19 ) (interval 16s nominal) 01101 = 1:262144 (2 18 ) (interval 8s nominal) 01100 = 1:131072 (2 17 ) (interval 4s nominal) 01011 = 1:65536 (interval 2s nominal) (reset value) 01010 = 1:32768 (interval 1s nominal) 01001 = 1:16384 (interval 512 ms nominal) 01000 = 1:8192 (interval 256 ms nominal) 00111 = 1:4096 (interval 128 ms nominal) 00110 = 1:2048 (interval 64 ms nominal) 00101 = 1:1024 (interval 32 ms nominal) 00100 = 1:512 (interval 16 ms nominal) 00011 = 1:256 (interval 8 ms nominal) 00010 = 1:128 (interval 4 ms nominal) 00001 = 1:64 (interval 2 ms nominal) 00000 = 1:32 (interval 1 ms nominal) bit 0 swdten: software enable/disable for watchdog timer bit if wdte<1:0> = 1x : this bit is ignored. if wdte<1:0> = 01 : 1 = wdt is turned on 0 = wdt is turned off if wdte<1:0> = 00 : this bit is ignored. note 1: times are approximate. wdt time is based on 31 khz lfintosc.
PIC12LF1552 ds41674b-page 74 preliminary ? 2013 microchip technology inc. table 9-3: summary of registers associated with watchdog timer table 9-4: summary of configuration word with watchdog timer name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page osccon pllen ircf<3:0> ?scs<1:0> 47 pcon stkovf stkunf ?rwdt rmclr ri por bor 55 status ? ? ?to pd z dc c 16 wdtcon ? ? wdtps<4:0> swdten 73 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by watchdog timer. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? ? ? clkouten boren<1:0> ? 36 7:0 cp mclre pwrte wdte<1:0> ? fosc<1:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by watchdog timer.
? 2013 microchip technology inc. preliminary ds41674b-page 75 PIC12LF1552 10.0 flash program memory control the flash program memory is readable and writable during normal operation over the full v dd range. program memory is indirectly addressed using special function registers (sfrs). the sfrs used to access program memory are: ?pmcon1 ?pmcon2 ?pmdatl ?pmdath ? pmadrl ?pmadrh when accessing the program memory, the pmdath:pmdatl register pair forms a 2-byte word that holds the 14-bit data for read/write, and the pmadrh:pmadrl register pair forms a 2-byte word that holds the 15-bit address of the program memory location being read. the write time is controlled by an on-chip timer. the write/ erase voltages are generated by an on-chip charge pump. the flash program memory can be protected in two ways; by code protection (cp bit in configuration words) and write protection (wrt<1:0> bits in configuration words). code protection (cp = 0 ) (1) , disables access, reading and writing, to the flash program memory via external device programmers. code protection does not affect the self-write and erase functionality. code protection can only be reset by a device programmer performing a bulk erase to the device, clearing all flash program memory, configuration bits and user ids. write protection prohibits self-write and erase to a portion or all of the flash program memory as defined by the bits wrt<1:0>. write protection does not affect a device programmers ability to read, write or erase the device. 10.1 pmadrl and pmadrh registers the pmadrh:pmadrl register pair can address up to a maximum of 16k words of program memory. when selecting a program address value, the msb of the address is written to the pmadrh register and the lsb is written to the pmadrl register. 10.1.1 pmcon1 and pmcon2 registers pmcon1 is the control register for flash program memory accesses. control bits rd and wr initiate read and write, respectively. these bits cannot be cleared, only set, in software. they are cleared by hardware at completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental, premature termination of a write operation. the wren bit, when set, will allow a write operation to occur. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a reset during normal operation. in these situations, following reset, the user can check the wrerr bit and execute the appropriate error handling routine. the pmcon2 register is a write-only register. attempting to read the pmcon2 register will return all ? 0 ?s. to enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the pmcon2 register. the required unlock sequence prevents inadvertent writes to the program memory write latches and flash program memory. 10.2 flash program memory overview it is important to understand the flash program memory structure for erase and programming operations. flash program memory is arranged in rows. a row consists of a fixed number of 14-bit program memory words. a row is the minimum size that can be erased by user software. after a row has been erased, the user can reprogram all or a portion of this row. data to be written into the program memory row is written to 14-bit wide data write latches. these write latches are not directly accessible to the user, but may be loaded via sequential writes to the pmdath:pmdatl register pair. see table 10-1 for erase row size and the number of write latches for flash program memory. note 1: code protection of the entire flash program memory array is enabled by clearing the cp bit of configuration words. note: if the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in ram prior to the erase. then, new data and retained data can be written into the write latches to reprogram the row of flash program memory. how- ever, any unprogrammed locations can be written without first erasing the row. in this case, it is not necessary to save and rewrite the other previously programmed locations. table 10-1: flash memory organization by device device row erase (words) write latches (words) PIC12LF1552 16 16
PIC12LF1552 ds41674b-page 76 preliminary ? 2013 microchip technology inc. 10.2.1 reading the flash program memory to read a program memory location, the user must: 1. write the desired address to the pmadrh:pmadrl register pair. 2. clear the cfgs bit of the pmcon1 register. 3. then, set control bit rd of the pmcon1 register. once the read control bit is set, the program memory flash controller will use the second instruction cycle to read the data. this causes the second instruction immediately following the ? bsf pmcon1,rd ? instruction to be ignored. the data is available in the very next cycle, in the pmdath:pmdatl register pair; therefore, it can be read as two bytes in the following instructions. pmdath:pmdatl register pair will hold this value until another read or until it is written to by the user. figure 10-1: flash program memory read flowchart note: the two instructions following a program memory read are required to be nop s. this prevents the user from executing a two-cycle instruction on the next instruction after the rd bit is set. start read operation select program or configuration memory (cfgs) select word address (pmadrh:pmadrl) end read operation instruction fetched ignored nop execution forced instruction fetched ignored nop execution forced initiate read operation (rd = 1 ) data read now in pmdath:pmdatl
? 2013 microchip technology inc. preliminary ds41674b-page 77 PIC12LF1552 figure 10-2: flash program me mory read cycle execution example 10-1: flash program memory read q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bsf pmcon1,rd executed here instr(pc + 1) executed here pc pc + 1 pmadrh,pmadrl pc+3 pc + 5 flash addr rd bit pmdath,pmdatl pc + 3 pc + 4 instr (pc + 1) instr(pc - 1) executed here instr(pc + 3) executed here instr(pc + 4) executed here flash data pmdath pmdatl register instr (pc) instr (pc + 3) instr (pc + 4) instruction ignored forced nop instr(pc + 2) executed here instruction ignored forced nop * this code block will read 1 word of program * memory at the memory address: prog_addr_hi: prog_addr_lo * data will be returned in the variables; * prog_data_hi, prog_data_lo banksel pmadrl ; select bank for pmcon registers movlw prog_addr_lo ; movwf pmadrl ; store lsb of address movlw prog_addr_hi ; movwf pmadrh ; store msb of address bcf pmcon1,cfgs ; do not select configuration space bsf pmcon1,rd ; initiate read nop ; ignored ( figure 10-2 ) nop ; ignored ( figure 10-2 ) movf pmdatl,w ; get lsb of word movwf prog_data_lo ; store in user location movf pmdath,w ; get msb of word movwf prog_data_hi ; store in user location
PIC12LF1552 ds41674b-page 78 preliminary ? 2013 microchip technology inc. 10.2.2 flash memory unlock sequence the unlock sequence is a mechanism that protects the flash program memory from unintended self-write programming or erasing. the sequence must be executed and completed without interruption to successfully complete any of the following operations: ?row erase ? load program memory write latches ? write of program memory write latches to program memory ? write of program memory write latches to user ids the unlock sequence consists of the following steps: 1. write 55h to pmcon2 2. write aah to pmcon2 3. set the wr bit in pmcon1 4. nop instruction 5. nop instruction once the wr bit is set, the processor will always force two nop instructions. when an erase row or program row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is complete and then resume with the next instruction. when the operation is loading the program memory write latches, the processor will always force the two nop instructions and continue uninterrupted with the next instruction. since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. figure 10-3: flash program memory unlock sequence flowchart write 055h to pmcon2 start unlock sequence write 0aah to pmcon2 initiate write or erase operation (wr = 1 ) instruction fetched ignored nop execution forced end unlock sequence instruction fetched ignored nop execution forced
? 2013 microchip technology inc. preliminary ds41674b-page 79 PIC12LF1552 10.2.3 erasing flash program memory while executing code, program memory can only be erased by rows. to erase a row: 1. load the pmadrh:pmadrl register pair with any address within the row to be erased. 2. clear the cfgs bit of the pmcon1 register. 3. set the free and wren bits of the pmcon1 register. 4. write 55h, then aah, to pmcon2 (flash programming unlock sequence). 5. set control bit wr of the pmcon1 register to begin the erase operation. see example 10-2 . after the ? bsf pmcon1,wr ? instruction, the processor requires two cycles to set up the erase operation. the user must place two nop instructions after the wr bit is set. the processor will halt internal operations for the typical 2 ms erase time. this is not sleep mode as the clocks and peripherals will continue to run. after the erase cycle, the processor will resume operation with the third instruction after the pmcon1 write instruction. figure 10-4: flash program memory erase flowchart disable interrupts (gie = 0 ) start erase operation select program or configuration memory (cfgs) select row address (pmadrh:pmadrl) select erase operation (free = 1 ) enable write/erase operation (wren = 1 ) unlock sequence (figure x-x) disable write/erase operation (wren = 0 ) re-enable interrupts (gie = 1 ) end erase operation cpu stalls while erase operation completes (2ms typical) figure 10-3
PIC12LF1552 ds41674b-page 80 preliminary ? 2013 microchip technology inc. example 10-2: erasing one row of program memory ; this row erase routine assumes the following: ; 1. a valid address within the erase row is loaded in addrh:addrl ; 2. addrh and addrl are located in shared data memory 0x70 - 0x7f (common ram) bcf intcon,gie ; disable ints so required sequences will execute properly banksel pmadrl movf addrl,w ; load lower 8 bits of erase address boundary movwf pmadrl movf addrh,w ; load upper 6 bits of erase address boundary movwf pmadrh bcf pmcon1,cfgs ; not configuration space bsf pmcon1,free ; specify an erase operation bsf pmcon1,wren ; enable writes movlw 55h ; start of required sequence to initiate erase movwf pmcon2 ; write 55h movlw 0aah ; movwf pmcon2 ; write aah bsf pmcon1,wr ; set wr bit to begin erase nop ; nop instructions are forced as processor starts nop ; row erase of program memory. ; ; the processor stalls until the erase process is complete ; after erase processor continues with 3rd instruction bcf pmcon1,wren ; disable writes bsf intcon,gie ; enable interrupts required sequence
? 2013 microchip technology inc. preliminary ds41674b-page 81 PIC12LF1552 10.2.4 writing to flash program memory program memory is programmed using the following steps: 1. load the address in pmadrh:pmadrl of the row to be programmed. 2. load each write latch with data. 3. initiate a programming operation. 4. repeat steps 1 through 3 until all data is written. before writing to program memory, the word(s) to be written must be erased or previously unwritten. program memory can only be erased one row at a time. no automatic erase occurs upon the initiation of the write. program memory can be written one or more words at a time. the maximum number of words written at one time is equal to the number of write latches. see figure 10-5 (row writes to program memory with 16 write latches) for more details. the write latches are aligned to the flash row address boundary defined by the upper 11-bits of pmadrh:pmadrl, (pmadrh<6:0>:pmadrl<7:4>) with the lower 4-bits of pmadrl, (pmadrl<3:0>) determining the write latch being loaded. write opera- tions do not cross these boundaries. at the completion of a program memory write operation, the data in the write latches is reset to contain 0x3fff. the following steps should be completed to load the write latches and program a row of program memory. these steps are divided into two parts. first, each write latch is loaded with data from the pmdath:pmdatl using the unlock sequence with lwlo = 1 . when the last word to be loaded into the write latch is ready, the lwlo bit is cleared and the unlock sequence executed. this initiates the programming operation, writing all the latches into flash program memory. 1. set the wren bit of the pmcon1 register. 2. clear the cfgs bit of the pmcon1 register. 3. set the lwlo bit of the pmcon1 register. when the lwlo bit of the pmcon1 register is ? 1 ?, the write sequence will only load the write latches and will not initiate the write to flash program memory. 4. load the pmadrh:pmadrl register pair with the address of the location to be written. 5. load the pmdath:pmdatl register pair with the program memory data to be written. 6. execute the unlock sequence ( section 10.2.2 ?flash memory unlock sequence? ). the write latch is now loaded. 7. increment the pmadrh:pmadrl register pair to point to the next location. 8. repeat steps 5 through 7 until all but the last write latch has been loaded. 9. clear the lwlo bit of the pmcon1 register. when the lwlo bit of the pmcon1 register is ? 0 ?, the write sequence will initiate the write to flash program memory. 10. load the pmdath:pmdatl register pair with the program memory data to be written. 11. execute the unlock sequence ( section 10.2.2 ?flash memory unlock sequence? ). the entire program memory latch content is now written to flash program memory. an example of the complete write sequence is shown in example 10-3 . the initial address is loaded into the pmadrh:pmadrl register pair; the data is loaded using indirect addressing. note: the special unlock sequence is required to load a write latch with data or initiate a flash programming operation. if the unlock sequence is interrupted, writing to the latches or program memory will not be initiated. note: the program memory write latches are reset to the blank state (0x3fff) at the completion of every write or erase operation. as a result, it is not necessary to load all the program memory write latches. unloaded latches will remain in the blank state.
PIC12LF1552 ds41674b-page 82 preliminary ? 2013 microchip technology inc. figure 10-5: block writes to flash prog ram memory with 16 write latches pmdath pmdatl 7 5 0 7 0 6 8 14 14 14 write latch #15 0fh 14 14 pmadrh pmadrl 7 6 0 7 5 4 0 program memory write latches 14 14 14 4 11 pmadrh<6:0> :pmadrl<7:4> flash program memory row row address decode addr write latch #14 0eh write latch #1 01h write latch #0 00h addr addr addr 000h 001fh 000eh 0000h 0001h 001h 001fh 001eh 0010h 0011h 002h 002fh 002eh 0020h 0021h 7feh 7fefh 7feeh 7fe0h 7fe1h 7ffh 7fffh 7ffeh 7ff0h 7ff1h 14 r9 r8 r7 r6 r5 r4 r3 - r1 r0 c3 c2 c1 c0 r2 pmadrl<4:0> 800h 8009h - 801fh 8000h - 8003h configuration words user id 0 - 3 8007h ? 8008h 8006h deviceid revid reserved 8004h - 8005h reserved configuration memory cfgs = 0 cfgs = 1 - - r10
? 2013 microchip technology inc. preliminary ds41674b-page 83 PIC12LF1552 figure 10-6: flash program memory write flowchart disable interrupts (gie = 0 ) start write operation select program or config. memory (cfgs) select row address (pmadrh:pmadrl) select write operation (free = 0 ) enable write/erase operation (wren = 1 ) unlock sequence (figure x-x) disable write/erase operation (wren = 0 ) re-enable interrupts (gie = 1 ) end write operation no delay when writing to program memory latches determine number of words to be written into program or configuration memory. the number of words cannot exceed the number of words per row. (word_cnt) load the value to write (pmdath:pmdatl) update the word counter (word_cnt--) last word to write ? increment address (pmadrh:pmadrl++) unlock sequence (figure x-x) cpu stalls while write operation completes (2ms typical) load write latches only (lwlo = 1 ) write latches to flash (lwlo = 0 ) no yes figure 10-3 figure 10-3
PIC12LF1552 ds41674b-page 84 preliminary ? 2013 microchip technology inc. example 10-3: writing to flash program memory ; this write routine assumes the following: ; 1. 32 bytes of data are loaded, starting at the address in data_addr ; 2. each word of data to be written is made up of two adjacent bytes in data_addr, ; stored in little endian format ; 3. a valid starting address (the least significant bits = 00000) is loaded in addrh:addrl ; 4. addrh and addrl are located in shared data memory 0x70 - 0x7f (common ram) ; bcf intcon,gie ; disable ints so required sequences will execute properly banksel pmadrh ; bank 3 movf addrh,w ; load initial address movwf pmadrh ; movf addrl,w ; movwf pmadrl ; movlw low data_addr ; load initial data address movwf fsr0l ; movlw high data_addr ; load initial data address movwf fsr0h ; bcf pmcon1,cfgs ; not configuration space bsf pmcon1,wren ; enable writes bsf pmcon1,lwlo ; only load write latches loop moviw fsr0++ ; load first data byte into lower movwf pmdatl ; moviw fsr0++ ; load second data byte into upper movwf pmdath ; movf pmadrl,w ; check if lower bits of address are '00000' xorlw 0x0f ; check if we're on the last of 16 addresses andlw 0x0f ; btfsc status,z ; exit if last of 16 words, goto start_write ; movlw 55h ; start of required write sequence: movwf pmcon2 ; write 55h movlw 0aah ; movwf pmcon2 ; write aah bsf pmcon1,wr ; set wr bit to begin write nop ; nop instructions are forced as processor ; loads program memory write latches nop ; incf pmadrl,f ; still loading latches increment address goto loop ; write next latches start_write bcf pmcon1,lwlo ; no more loading latches - actually start flash program ; memory write movlw 55h ; start of required write sequence: movwf pmcon2 ; write 55h movlw 0aah ; movwf pmcon2 ; write aah bsf pmcon1,wr ; set wr bit to begin write nop ; nop instructions are forced as processor writes ; all the program memory write latches simultaneously nop ; to program memory. ; after nops, the processor ; stalls until the self-write process in complete ; after write processor continues with 3rd instruction bcf pmcon1,wren ; disable writes bsf intcon,gie ; enable interrupts required sequence required sequence
? 2013 microchip technology inc. preliminary ds41674b-page 85 PIC12LF1552 10.3 modifying flash program memory when modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a ram image. program memory is modified using the following steps: 1. load the starting address of the row to be modified. 2. read the existing data from the row into a ram image. 3. modify the ram image to contain the new data to be written into program memory. 4. load the starting address of the row to be rewritten. 5. erase the program memory row. 6. load the write latches with data from the ram image. 7. initiate a programming operation. figure 10-7: flash program memory modify flowchart start modify operation read operation (figure x.x) erase operation (figure x.x) modify image the words to be modified are changed in the ram image end modify operation write operation use ram image (figure x.x) an image of the entire row read must be stored in ram figure 10-2 figure 10-4 figure 10-5
PIC12LF1552 ds41674b-page 86 preliminary ? 2013 microchip technology inc. 10.4 user id, device id and configuration word access instead of accessing program memory, the user id?s, device id/revision id and configuration words can be accessed when cfgs = 1 in the pmcon1 register. this is the region that would be pointed to by pc<15> = 1 , but not all addresses are accessible. different access may exist for reads and writes. refer to tab le 1 0- 2 . when read access is initiated on an address outside the parameters listed in tab le 1 0- 2 , the pmdath:pmdatl register pair is cleared, reading back ? 0 ?s. table 10-2: user id, device id and configuration word access (cfgs = 1 ) example 10-4: conf iguration word and device id access address function read access write access 8000h-8003h user ids yes yes 8006h device id/revision id yes no 8007h-8008h configuration words 1 and 2 yes no * this code block will read 1 word of program memory at the memory address: * prog_addr_lo (must be 00h-08h) data will be returned in the variables; * prog_data_hi, prog_data_lo banksel pmadrl ; select correct bank movlw prog_addr_lo ; movwf pmadrl ; store lsb of address clrf pmadrh ; clear msb of address bsf pmcon1,cfgs ; select configuration space bcf intcon,gie ; disable interrupts bsf pmcon1,rd ; initiate read nop ; executed (see figure 10-2 ) nop ; ignored (see figure 10-2 ) bsf intcon,gie ; restore interrupts movf pmdatl,w ; get lsb of word movwf prog_data_lo ; store in user location movf pmdath,w ; get msb of word movwf prog_data_hi ; store in user location
? 2013 microchip technology inc. preliminary ds41674b-page 87 PIC12LF1552 10.5 write verify it is considered good programming practice to verify that program memory writes agree with the intended value. since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in ram after the last write is complete. figure 10-8: flash program memory verify flowchart start verify operation read operation (figure x.x) end verify operation this routine assumes that the last row of data written was from an image saved in ram. this image will be used to verify the data currently stored in flash program memory. pmdat = ram image ? last word ? fail verify operation no yes yes no figure 10-2
PIC12LF1552 ds41674b-page 88 preliminary ? 2013 microchip technology inc. 10.6 register definitions: flash program memory control register 10-1: pmdatl: program memory data low byte register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u pmdat<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 pmdat<7:0> : read/write value for least significant bits of program memory register 10-2: pmdath: program memory data high byte register u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u ? ? pmdat<13:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 pmdat<13:8> : read/write value for most significant bits of program memory register 10-3: pmadrl: program me mory address low byte register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 pmadr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 pmadr<7:0> : specifies the least significant bits for program memory address register 10-4: pmadrh: program memory address high byte register u-1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? (1) pmadr<14:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 1 ? bit 6-0 pmadr<14:8> : specifies the most significant bits for program memory address note 1: unimplemented bit, read as ? 1 ?.
? 2013 microchip technology inc. preliminary ds41674b-page 89 PIC12LF1552 register 10-5: pmcon1: progra m memory control 1 register u-1 r/w-0/0 r/w-0/0 r/w/hc-0/0 r/w/hc-x/q (2) r/w-0/0 r/s/hc-0/0 r/s/hc-0/0 ? (1) cfgs lwlo free wrerr wren wr rd bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cl eared hc = bit is cleared by hardware bit 7 unimplemented: read as ? 1 ? bit 6 cfgs: configuration select bit 1 = access configuration, user id and device id registers 0 = access flash program memory bit 5 lwlo: load write latches only bit (3) 1 = only the addressed program memory write latch is loaded/updated on the next wr command 0 = the addressed program memory write latch is loaded/ updated and a write of all program memory write latches will be initiated on the next wr command bit 4 free: program flash erase enable bit 1 = performs an erase operation on the next wr command (hardware cleared upon completion) 0 = performs an write operation on the next wr command bit 3 wrerr: program/erase error flag bit 1 = condition indicates an improper program or erase sequenc e attempt or termination (bit is set automatically on any set attempt (write ? 1 ?) of the wr bit). 0 = the program or erase operation completed normally bit 2 wren: program/erase enable bit 1 = allows program/erase cycles 0 = inhibits programming/erasing of program flash bit 1 wr: write control bit 1 = initiates a program flash program/erase operation. the operation is self-timed and the bit is cl eared by hardware once operation is complete. the wr bit can only be set (not cleared) in software. 0 = program/erase operation to the flash is complete and inactive bit 0 rd: read control bit 1 = initiates a program flash read. read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. 0 = does not initiate a program flash read note 1: unimplemented bit, read as ? 1 ?. 2: the wrerr bit is automatically set by hardware when a program memory writ e or erase operation is started (wr = 1 ). 3: the lwlo bit is ignored during a progr am memory erase operation (free = 1 ).
PIC12LF1552 ds41674b-page 90 preliminary ? 2013 microchip technology inc. table 10-3: summary of registers as sociated with flash program memory table 10-4: summary of configuration word with flash program memory register 10-6: pmcon2: progra m memory control 2 register w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 program memory control register 2 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 flash memory unlock pattern bits to unlock writes, a 55h must be written first, followed by an aah, before setting the wr bit of the pmcon1 register. the value written to this register is used to unlock the writes. there are specific timing requirements on these writes. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 62 pmcon1 ? (1) cfgs lwlo free wrerr wren wr rd 89 pmcon2 program memory control register 2 90 pmadrl pmadrl<7:0> 88 pmadrh ? (1) pmadrh<6:0> 88 pmdatl pmdatl<7:0> 88 pmdath ? ? pmdath<5:0> 88 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by flash program memory module. note 1: unimplemented, read as ? 1 ?. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? ? ? clkouten boren<1:0> ? 36 7:0 cp mclre pwrte wdte<1:0> ? fosc<1:0> config2 13:8 ? ? lvp ? lpbor borv stvren ? 37 7:0 ? ? ? ? ? ?wrt<1:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by flash program memory.
? 2013 microchip technology inc. preliminary ds41674b-page 91 PIC12LF1552 11.0 i/o ports each port has three standard registers for its operation. these registers are: ? trisx registers (data direction) ? portx registers (reads the levels on the pins of the device) ? latx registers (output latch) some ports may have one or more of the following additional registers. these registers are: ? anselx (analog select) ? wpux (weak pull-up) in general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. however, the pin can still be read. the data latch (latx registers) is useful for read-modify-write operations on the value that the i/o pins are driving. a write operation to the latx register has the same effect as a write to the corresponding portx register. a read of the latx register reads of the values held in the i/o port latches, while a read of the portx register reads the actual i/o pin value. ports that support analog inputs have an associated anselx register. when an ansel bit is set, the digital input buffer associated with that bit is disabled. disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. a simplified model of a generic i/o port, without the interfaces to other peripherals, is shown in figure 11-1 . figure 11-1: generic i/o port operation example 11-1: initializing porta table 11-1: port availability per device device porta PIC12LF1552 q d ck write latx data register i/o pin read portx write portx trisx read latx data bus to digital peripherals anselx v dd v ss to analog peripherals ; this code example illustrates ; initializing the porta register. the ; other ports are initialized in the same ; manner. banksel porta ; clrf porta ;init porta banksel lata ;data latch clrf lata ; banksel ansela ; clrf ansela ;digital i/o banksel trisa ; movlw b'00111000' ;set ra<5:3> as inputs movwf trisa ;and set ra<2:0> as ;outputs
PIC12LF1552 ds41674b-page 92 preliminary ? 2013 microchip technology inc. 11.1 alternate pin function the alternate pin function control (apfcon) register is used to steer specific peripheral input and output functions between different pins. the apfcon register is shown in register 11-1 . for this device family, the following functions can be moved between different pins. ?sdo ?ss ? sda/sdi these bits have no effect on the values of any tris register. port and tris overrides will be routed to the correct pin. the unselected pin will be unaffected. 11.2 register definitions: alternate pin function control register 11-1: apfcon: alternat e pin function co ntrol register r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 ? sdosel sssel sdsel ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6 sdosel: pin selection bit 1 = sdo function is on ra4 0 = sdo function is on ra0 bit 5 sssel: pin selection bit 1 =ss function is on ra0 0 =ss function is on ra3 bit 4 sdsel: pin selection bit 1 = sda/sdi function is on ra3 (1) 0 = sda/sdi function is on ra2 bit 3-0 unimplemented: read as ? 0 ? note 1: the mssp module has the ability to output low on ra3 when it is used as sda/sdi.
? 2013 microchip technology inc. preliminary ds41674b-page 93 PIC12LF1552 11.3 porta registers 11.3.1 data register porta is a 6-bit wide, bidirectional port. the corresponding data direction register is trisa ( register 11-3 ). setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., disable the output driver). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). the exception is ra3, which is input-only and its tris bit will always read as ? 1 ?. example 11-1 shows how to initialize an i/o port. reading the porta register ( register 11-2 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (lata). 11.3.2 direction control the trisa register ( register 11-3 ) controls the porta pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisa register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. 11.3.3 ansela register the ansela register ( register 11-5 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate ansela bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the ansela bits has no effect on digital output functions. a pin with tris clear and ansel set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. 11.3.4 porta functions and output priorities each porta pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 11-2 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input functions, such as adc inputs, are not shown in the priority lists. these inputs are active when the i/o pin is set for analog mode using the anselx registers. digital output functions may control the pin when it is in analog mode with the priority shown in table 11-2 . note: the ansela bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to ? 0 ? by user software. table 11-2: porta output priority pin name function priority (1) ra0 icspdat sdo (2) ss (3) ra0 ra1 scl sck ra1 ra2 adout sda (2) sdi (2) ra2 ra3 sda (3) sdi (3) ss (2) ra3 ra4 clkout sdo (3) adgrda ra4 ra5 adgrdb ra5 note 1: priority listed from highest to lowest. 2: default pin (see apfcon register). 3: alternate pin (see apfcon register).
PIC12LF1552 ds41674b-page 94 preliminary ? 2013 microchip technology inc. 11.4 register definitions: porta register 11-2: porta: porta register u-0 u-0 r/w-x/x r/w-x/x r-x/x r/w-x/x r/w-x/x r/w-x/x ? ? ra5 ra4 ra3 ra2 ra1 ra0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 ra<5:0> : porta i/o value bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to porta are actually written to corresponding lata register. reads from porta register is return of actual i/o pin values. register 11-3: trisa: porta tri-state register u-0 u-0 r/w-1/1 r/w-1/1 u-1 r/w-1/1 r/w-1/1 r/w-1/1 ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-4 trisa<5:4>: porta tri-state control bit 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output bit 3 unimplemented: read as ? 1 ? bit 2-0 trisa<2:0>: porta tri-state control bit 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output note 1: unimplemented, read as ? 1 ?.
? 2013 microchip technology inc. preliminary ds41674b-page 95 PIC12LF1552 register 11-4: lata: porta data latch register u-0 u-0 r/w-x/u r/w-x/u u-0 r/w-x/u r/w-x/u r/w-x/u ? ?lata5lata4 ? lata2 lata1 lata0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-4 lata<5:4> : ra<5:4> output latch value bits (1) bit 3 unimplemented: read as ? 0 ? bit 2-0 lata<2:0> : ra<2:0> output latch value bits (1) note 1: writes to porta are actually written to corresponding lata register. reads from porta register is return of actual i/o pin values. register 11-5: ansela: porta analog select register u-0 u-0 r/w-1/1 r/w-1/1 u-0 r/w-1/1 r/w-1/1 r/w-1/1 ? ? ansa5 ansa4 ? ansa2 ansa1 ansa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-4 ansa<5:4> : analog select between analog or digital function on pins ra<5:4>, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. bit 3 unimplemented: read as ? 0 ? bit 2-0 ansa<2:0> : analog select between analog or digital function on pins ra<2:0>, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin.
PIC12LF1552 ds41674b-page 96 preliminary ? 2013 microchip technology inc. table 11-3: summary of regist ers associated with porta table 11-4: summary of conf iguration word with porta register 11-6: wpua: weak pull-up porta register u-0 u-0 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 ? ? wpua5 wpua4 wpua3 wpua2 wpua1 wpua0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 wpua<5:0> : weak pull-up register bits (3) 1 = pull-up enabled 0 = pull-up disabled note 1: global wpuen bit of the option_reg register must be cleared for individual pull-ups to be enabled. 2: the weak pull-up device is automatically disabled if the pin is in configured as an output. 3: for the wpua3 bit, when mclre = 1 , weak pull-up is internally enabled, but not reported here. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ansa5 ansa4 ? ansa2 ansa1 ansa0 95 apfcon ? sdosel sssel sdsel ? ? ? ? 92 lata ? ?lata5lata4 ? lata2 lata1 lata0 95 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 140 porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 94 trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 94 wpua ? ? wpua5 wpua4 wpua3 wpua2 wpua1 wpua0 96 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by porta. note 1: unimplemented, read as ? 1 ?. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? ? ?clkouten boren<1:0> ? 36 7:0 cp mclre pwrte wdte<1:0> ? fosc<1:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by porta.
? 2013 microchip technology inc. preliminary ds41674b-page 97 PIC12LF1552 12.0 interrupt-on-change the porta pins can be configured to operate as interrupt-on-change (ioc) pins. an interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. any individual port pin, or combination of port pins, can be configured to generate an interrupt. the interrupt-on-change module has the following features: ? interrupt-on-change enable (master switch) ? individual pin configuration ? rising and falling edge detection ? individual pin interrupt flags figure 12-1 is a block diagram of the ioc module. 12.1 enabling the module to allow individual port pins to generate an interrupt, the iocie bit of the intcon register must be set. if the iocie bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. 12.2 individual pin configuration for each port pin, a rising edge detector and a falling edge detector are present. to enable a pin to detect a rising edge, the associated bit of the iocxp register is set. to enable a pin to detect a falling edge, the associated bit of the iocxn register is set. a pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the iocxp and iocxn registers, respectively. 12.3 interrupt flags the iocafx bits located in the iocaf register, respectively, are status flags that correspond to the interrupt-on-change pins of the associated port. if an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the iocie bit is set. the iocif bit of the intcon register reflects the status of all iocafx bits. 12.4 clearing interrupt flags the individual status flags, (iocafx bits), can be cleared by resetting them to zero. if another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. in order to ensure that no detected edge is lost while clearing flags, only and operations masking out known changed bits should be performed. the following sequence is an example of what should be performed. example 12-1: clearing interrupt flags (porta example) 12.5 operation in sleep the interrupt-on-change interrupt sequence will wake the device from sleep mode, if the iocie bit is set. if an edge is detected while in sleep mode, the iocxf register will be updated prior to the first instruction executed out of sleep. movlw 0xff xorwf iocaf, w andwf iocaf, f
PIC12LF1552 ds41674b-page 98 preliminary ? 2013 microchip technology inc. figure 12-1: interrupt-on-change bl ock diagram (porta example) d ck r q d ck r q rax iocanx iocapx q2 d ck s q q4q1 data bus = 0 or 1 write iocafx iocie to data bus iocafx edge detect ioc interrupt to cpu core from all other iocafx individual pin detectors q1 q2 q3 q4 q4q1 q1 q2 q3 q4 q1 q2 q3 q4 q4 q4q1 q4q1 q4q1
? 2013 microchip technology inc. preliminary ds41674b-page 99 PIC12LF1552 12.6 register definitions: interrupt-on-change control register 12-1: iocap: interrupt-on-c hange porta positive edge register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 iocap<5:0>: interrupt-on-change porta positive edge enable bits 1 = interrupt-on-change enabled on the pin for a positive going edge. iocafx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin. register 12-2: iocan: interrupt-on-change porta negative edge register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 iocan<5:0>: interrupt-on-change porta negative edge enable bits 1 = interrupt-on-change enabled on the pin for a negative going edge. iocafx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin. register 12-3: iocaf: interrupt- on-change porta flag register u-0 u-0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 ? ? iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hs - bit is set in hardware bit 7-6 unimplemented: read as ? 0 ? bit 5-0 iocaf<5:0>: interrupt-on-change porta flag bits 1 = an enabled change was detected on the associated pin. set when iocapx = 1 and a rising edge was detected on rax, or when iocanx = 1 and a falling edge was detected on rax. 0 = no change was detected, or the user cleared the detected change
PIC12LF1552 ds41674b-page 100 preliminary ? 2013 microchip technology inc. table 12-1: summary of registers as sociated with interrupt-on-change name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ansa5 ansa4 ? ansa2 ansa1 ansa0 95 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 62 iocaf ? ? iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 99 iocan ? ? iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 99 iocap ? ? iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 99 trisa ? ? trisa5 trisa4 ?(1) trisa2 trisa1 trisa0 94 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by interrupt-on-change. note 1: unimplemented, read as ? 1 ?.
? 2013 microchip technology inc. preliminary ds41674b-page 101 PIC12LF1552 13.0 fixed voltage reference (fvr) the fixed voltage reference, or fvr, is a stable voltage reference, independent of v dd , with 1.024v and 2.048v selectable output levels. the output of the fvr can be configured as the fvr input channel on the adc. the fvr can be enabled by setting the fvren bit of the fvrcon register. 13.1 independent gain amplifier the output of the fvr supplied to the adc is routed through a programmable gain amplifier. each amplifier can be programmed for a gain of 1x or 2x, to produce the two possible voltage levels. the adfvr<1:0> bits of the fvrcon register are used to enable and configure the gain amplifier settings for the reference supplied to the adc module. refer- ence section 16.0 ?hardware capacitive voltage divider (cvd) module? for additional information. 13.2 fvr stabilization period when the fixed voltage reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. once the circuits stabilize and are ready for use, the fvrrdy bit of the fvrcon register will be set. see section 21.0 ?electrical specifications? for the minimum delay requirement. figure 13-1: voltage reference block diagram fvr buffer1 (to adc module) x1 x2 + - 1.024v fixed reference fvren fvrrdy 2 adfvr<1:0> any peripheral requiring the fixed reference (see table 13-1 ) table 13-1: peripherals requiring the fixed voltage reference (fvr) peripheral conditions description hfintosc fosc<1:0> = 00 and ircf<3:0> = 000x intosc is active and device is not in sleep. bor boren<1:0> = 11 bor always enabled. boren<1:0> = 10 and borfs = 1 bor disabled in sleep mode, bor fast start enabled. boren<1:0> = 01 and borfs = 1 bor under software control, bor fast start enabled.
PIC12LF1552 ds41674b-page 102 preliminary ? 2013 microchip technology inc. 13.3 register definitions: fvr control table 13-2: summary of registers associated with the fixed voltage reference register 13-1: fvrcon: fixed voltage reference control register r/w-0/0 r-q/q r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 fvren fvrrdy (1) tsen tsrng ? ?adfvr<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 fvren: fixed voltage reference enable bit 1 = fixed voltage reference is enabled 0 = fixed voltage reference is disabled bit 6 fvrrdy: fixed voltage reference ready flag bit (1) 1 = fixed voltage reference output is ready for use 0 = fixed voltage reference output is not ready or not enabled bit 5 tsen: temperature indicator enable bit (3) 1 = temperature indicator is enabled 0 = temperature indicator is disabled bit 4 tsrng: temperature indicator range selection bit (3) 1 =v out = v dd - 4v t (high range) 0 =v out = v dd - 2v t (low range) bit 3-2 unimplemented: read as ? 0 ? bit 1-0 adfvr<1:0>: adc fixed voltage reference selection bit 11 = adc fixed voltage reference peripheral output is off 10 = adc fixed voltage reference peripheral output is 2x (2.048v) (2) 01 = adc fixed voltage reference peripheral output is 1x (1.024v) 00 = adc fixed voltage reference peripheral output is off note 1: fvrrdy is always ? 1 ? for the PIC12LF1552 devices. 2: fixed voltage reference output cannot exceed v dd . 3: see section 14.0 ?temperature indicator module? for additional information. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page fvrcon fvren fvrrdy tsen tsrng ? ?adfvr<1:0> 102 legend: shaded cells are unused by the fixed voltage reference module.
? 2013 microchip technology inc. preliminary ds41674b-page 103 PIC12LF1552 14.0 temperature indicator module this family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. the circuit?s range of operating temperature falls between -40c and +85c. the output is a voltage that is proportional to the device temperature. the output of the temperature indicator is internally connected to the device adc. the circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. a one- point calibration allows the circuit to indicate a temperature closely surrounding that point. a two-point calibration allows the circuit to sense the entire range of temperature more accurately. reference application note an1333, ? use and calibration of the internal temperature indicator ? (ds01333) for more details regarding the calibration process. 14.1 circuit operation figure 14-1 shows a simplified block diagram of the temperature circuit. the proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. equation 14-1 describes the output characteristics of the temperature indicator. equation 14-1: v out ranges the temperature sense circuit is integrated with the fixed voltage reference (fvr) module. see section 13.0 ?fixed voltage reference (fvr)? for more information. the circuit is enabled by setting the tsen bit of the fvrcon register. when disabled, the circuit draws no current. the circuit operates in either high or low range. the high range, selected by setting the tsrng bit of the fvrcon register, provides a wider output voltage. this provides more resolution over the temperature range, but may be less consistent from part to part. this range requires a higher bias voltage to operate and thus, a higher v dd is needed. the low range is selected by clearing the tsrng bit of the fvrcon register. the low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. the low range is provided for low voltage operation. figure 14-1: temperature circuit diagram 14.2 minimum operating v dd when the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. when the temperature circuit is operated in high range, the device operating voltage, v dd , must be high enough to ensure that the temperature circuit is correctly biased. table 14-1 shows the recommended minimum v dd vs. range setting. table 14-1: recommended v dd vs. range 14.3 temperature output the output of the circuit is measured using the internal analog-to-digital converter. a channel is reserved for the temperature circuit output. refer to section 16.0 ?hardware capacitive voltage divider (cvd) module? for detailed information. 14.4 adc acquisition time to ensure accurate temperature measurements, the user must wait at least 200 ? s after the adc input multiplexer is connected to the temperature indicator output before the conversion is performed. in addition, the user must wait 200 ? s between sequential conversions of the temperature indicator output. high range: v out = v dd - 4v t low range: v out = v dd - 2v t min. v dd , tsrng = 1 min. v dd , tsrng = 0 3.6v 1.8v tsen tsrng v dd v out to a d c
PIC12LF1552 ds41674b-page 104 preliminary ? 2013 microchip technology inc. table 14-2: summary of registers associated with the temperature indicator name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page fvrcon fvren fvrrdy tsen tsrng ? adfvr<1:0> 118 legend: shaded cells are unused by the temperature indicator module.
? 2013 microchip technology inc. preliminary ds41674b-page 105 PIC12LF1552 15.0 analog-to-digital converter (adc) module the analog-to-digital converter (adc) allows conversion of an analog input signal to a 10-bit binary representation of that signal. this device uses analog inputs, which are multiplexed into a single sample and hold circuit. the output of the sample and hold is connected to the input of the converter. the converter generates a 10-bit binary result via successive approximation and stores the conversion result into the adc result registers (adresh:adresl register pair). figure 15-1 shows the block diagram of the adc. the adc voltage reference is software selectable to be either internally generated or externally supplied. the adc can generate an interrupt upon completion of a conversion. this interrupt can be used to wake-up the device from sleep. figure 15-1: adc block diagram note 1: when adon = 0 , all multiplexer inputs are disconnected. 2: see aadcon0 register ( register 16-1 ) for detailed analog channel selection per device. 3: adres0h and aadres0h are the same register in two locations, bank 1 and bank 14. see table 3-3 . 4: adres0l and aadres0l are the same register in two locations, bank 1 and bank 14. see table 3-3 . v dd v ref + adpref = 10 adpref = 0x fvr fvr buffer1 adon (1) go/done v ss adc 00000 00001 00010 00011 chs<4:0> (2) an0 an1 an2 v ref +/an3 11111 adresxl (4) 10 16 adfm 0 = left justify 1 = right justify temp indicator 11101 reserved adpref = 11 an4 reserved 00100 00101 11001 vrefh (adc positive reference) 11010 adresxh (3) 11011 11100 reserved reserved 11110 reserved
PIC12LF1552 ds41674b-page 106 preliminary ? 2013 microchip technology inc. 15.1 adc configuration when configuring and using the adc, the following functions must be considered: ? port configuration ? channel selection ? adc voltage reference selection ? adc conversion clock source ? interrupt control ? result formatting 15.1.1 port configuration the adc can be used to convert both analog and digital signals. when converting analog signals, the i/o pin should be configured for analog by setting the associated tris and ansel bits. refer to section 11.0 ?i/o ports? for more information. 15.1.2 channel selection there are up to eight channel selections available: ? an<4:0> pins ?v ref + (adc positive reference) ? temperature indicator ? fvr (fixed voltage reference) output refer to section 13.0 ?fixed voltage reference (fvr)? and section 14.0 ?temperature indicator module? for more information on these channel selec- tions. the chs bits of the adcon0 register determine which channel is connected to the sample and hold circuit. when changing channels, a delay is required before starting the next conversion. refer to section 16.1 ?hardware cvd operation? for more information. 15.1.3 adc voltage reference the adpref bits of the adcon1 register provides control of the positive voltage reference. the positive voltage reference can be: ?v ref + pin ?v dd ? fvr (fixed voltage reference) see section 13.0 ?fixed voltage reference (fvr)? for more details on the fixed voltage reference. 15.1.4 conversion clock the source of the conversion clock is software select- able via the adcs bits of the adcon1 register. there are seven possible clock options: ?f osc /2 ?f osc /4 ?f osc /8 ?f osc /16 ?f osc /32 ?f osc /64 ?f rc (dedicated internal oscillator) the time to complete one bit conversion is defined as t ad . one full 10-bit conversion requires 11.5 t ad periods as shown in figure 15-2 . for correct conversion, the appropriate t ad specifica- tion must be met. refer to the adc conversion require- ments in section 21.0 ?electrical specifications? for more information. table 15-1 gives examples of appropriate adc clock selections. note: analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. note: unless using the f rc , any changes in the system clock frequency will change the adc clock frequency, which may adversely affect the adc result.
? 2013 microchip technology inc. preliminary ds41674b-page 107 PIC12LF1552 table 15-1: adc clock period (t ad ) v s . device operating frequencies figure 15-2: analog-to-dig ital conversion t ad cycles adc clock period (t ad ) device frequency (f osc ) adc clock source adcs<2:0> 20 mhz 16 mhz 8 mhz 4 mhz 1 mhz fosc/2 000 100 ns (2) 125 ns (2) 250 ns (2) 500 ns (2) 2.0 ? s fosc/4 100 200 ns (2) 250 ns (2) 500 ns (2) 1.0 ? s4.0 ? s fosc/8 001 400 ns (2) 0.5 ? s (2) 1.0 ? s2.0 ? s 8.0 ? s (3) fosc/16 101 800 ns 1.0 ? s2.0 ? s4.0 ? s 16.0 ? s (3) fosc/32 010 1.6 ? s2.0 ? s4.0 ? s 8.0 ? s (3) 32.0 ? s (3) fosc/64 110 3.2 ? s4.0 ? s 8.0 ? s (3) 16.0 ? s (3) 64.0 ? s (3) f rc x11 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) legend: shaded cells are outside of recommended range. note 1: the f rc source has a typical t ad time of 1.6 ? s for v dd . 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: the adc clock period (t ad ) and total adc conversion time can be minimized when the adc clock is derived from the system clock f osc . however, the f rc clock source must be used when conversions are to be performed with the device in sleep mode. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy - t ad adresh:adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 on the following cycle:
PIC12LF1552 ds41674b-page 108 preliminary ? 2013 microchip technology inc. 15.1.5 interrupts the adc module allows for the ability to generate an interrupt upon completion of an analog-to-digital conversion. the adc interrupt flag is the adif bit in the pir1 register. the adc interrupt enable is the adie bit in the pie1 register. the adif bit must be cleared in software. this interrupt can be generated while the device is operating or while in sleep. if the device is in sleep, the interrupt will wake-up the device. upon waking from sleep, the next instruction following the sleep instruc- tion is always executed. if the user is attempting to wake-up from sleep and resume in-line code execu- tion, the gie and peie bits of the intcon register must be disabled. if the gie and peie bits of the intcon register are enabled, execution will switch to the interrupt service routine. 15.1.6 result formatting the 10-bit adc conversion result can be supplied in two formats, left justified or right justified. the adfm bit of the adcon1 register controls the output format. figure 15-3 shows the two output formats. figure 15-3: 10-bit adc conv ersion result format note 1: the adif bit is set at the completion of every conversion, regardless of whether or not the adc interrupt is enabled. 2: the adc operates during sleep only when the f rc oscillator is selected. adresh adresl (adfm = 0 )msb lsb bit 7 bit 0 bit 7 bit 0 10-bit adc result unimplemented: read as ? 0 ? (adfm = 1 ) msb lsb bit 7 bit 0 bit 7 bit 0 unimplemented: read as ? 0 ? 10-bit adc result
? 2013 microchip technology inc. preliminary ds41674b-page 109 PIC12LF1552 15.2 adc operation 15.2.1 starting a conversion to enable the adc module, the adon bit of the adcon0 register must be set to a ? 1 ?. setting the go/ done bit of the adcon0 register to a ? 1 ? will start the analog-to-digital conversion. 15.2.2 completion of a conversion when the conversion is complete, the adc module will: ? clear the go/done bit ? set the adif interrupt flag bit ? update the adresh and adresl registers with new conversion result 15.2.3 terminating a conversion if a conversion must be terminated before completion, the go/done bit can be cleared in software. the adresh and adresl registers will be updated with the partially complete analog-to-digital conversion sample. incomplete bits will match the last bit converted. 15.2.4 adc operation during sleep the adc module can operate during sleep. this requires the adc clock source to be set to the f rc option. when the f rc clock source is selected, the adc waits one additional instruction before starting the conversion. this allows the sleep instruction to be executed, which can reduce system noise during the conversion. if the adc interrupt is enabled, the device will wake-up from sleep when the conversion completes. if the adc interrupt is disabled, the adc module is turned off after the conversion completes, although the adon bit remains set. when the adc clock source is something other than f rc , a sleep instruction causes the present conver- sion to be aborted and the adc module is turned off, although the adon bit remains set. 15.2.5 special event trigger the special event trigger allows periodic adc measurements without software intervention, using the trigsel bits of the aadcon2 register. when this trigger occurs, the go/done bit is set by hardware from the timer0 overflow. using the special event trigger does not assure proper adc timing. it is the user?s responsibility to ensure that the adc timing requirements are met. refer to section 17.0 ?timer0 module? for more information. note: the go/done bit should not be set in the same instruction that turns on the adc. refer to section 15.2.6 ?adc conver- sion procedure? . note: a device reset forces all registers to their reset state. thus, the adc module is turned off and any pending conversion is terminated. table 15-2: special event trigger device source PIC12LF1552 tmr0
PIC12LF1552 ds41674b-page 110 preliminary ? 2013 microchip technology inc. 15.2.6 adc conversion procedure this is an example procedure for using the adc to perform an analog-to-digital conversion: 1. configure port: ? disable pin output driver (refer to the tris register) ? configure pin as analog (refer to the ansel register) 2. configure the adc module: ? select adc conversion clock ? configure voltage reference ? select adc input channel ? turn on adc module 3. configure adc interrupt (optional): ? clear adc interrupt flag ? enable adc interrupt ? enable peripheral interrupt ? enable global interrupt (1) 4. wait the required acquisition time (2) . 5. start conversion by setting the go/done bit. 6. wait for adc conversion to complete by one of the following: ? polling the go/done bit ? waiting for the adc interrupt (interrupts enabled) 7. read adc result in adres0h and adres0l. 8. clear the adc interrupt flag (required if interrupt is enabled). example 15-1: adc conversion note 1: the global interrupt can be disabled if the user is attempting to wake-up from sleep and resume in-line code execution. 2: refer to section 15.4 ?adc acquisi- tion requirements? . ;this code block configures the adc ;for polling, vdd and vss references, frc ;clock and an0 input. ; ;conversion start & polling for completion ; are included. ; banksel adcon1 ; movlw b?11110000? ;right justify, frc ;clock movwf adcon1 ;vdd and vss vref banksel trisa ; bsf trisa,0 ;set ra0 to input banksel ansel ; bsf ansel,0 ;set ra0 to analog banksel adcon0 ; movlw b?00000001? ;select channel an0 movwf adcon0 ;turn adc on call sampletime ;acquisiton delay bsf adcon0,adgo ;start conversion btfsc adcon0,adgo ;is conversion done? goto $-1 ;no, test again banksel adres0h ; movf adres0h,w ;read upper 2 bits movwf resulthi ;store in gpr space banksel adres0l ; movf adres0l,w ;read lower 8 bits movwf resultlo ;store in gpr space
? 2013 microchip technology inc. preliminary ds41674b-page 111 PIC12LF1552 15.3 adc register definitions the following registers are used to control the operation of the adc. register 15-1: adcon0: ad c control register 0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? chs<4:0> go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-2 chs<4:0>: analog channel select bits 11111 = fvr (fixed voltage reference) buffer 1 output (1) 11110 = reserved. no channel connected. 11101 = temperature indicator (2) . 11100 = reserved. no channel connected. 11011 = reserved. no channel connected. 11010 =v refh (adc positive reference) 11001 = reserved. no channel connected. ? ? ? 00101 = reserved. no channel connected. 00100 =an4 00011 =an3 00010 =an2 00001 =an1 00000 =an0 bit 1 go/done : adc conversion status bit 1 = adc conversion cycle in progress. setting this bit starts an adc conversion cycle. this bit is automatically cleared by hardware when the adc conversion has completed. 0 = adc conversion completed/not in progress bit 0 adon: adc enable bit 1 = adc is enabled 0 = adc is disabled and consumes no operating current note 1: see section 13.0 ?fixed voltage reference (fvr)? for more information. 2: see section 14.0 ?temperature indicator module? for more information.
PIC12LF1552 ds41674b-page 112 preliminary ? 2013 microchip technology inc. register 15-2: adcon1: ad c control register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 adfm adcs<2:0> ? ? adpref<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 adfm: adc result format select bit 1 = right justified. six most significant bits of adresh are set to ? 0 ? when the conversion result is loaded. 0 = left justified. six least significant bits of adresl are set to ? 0 ? when the conversion result is loaded. bit 6-4 adcs<2:0>: adc conversion clock select bits 000 =f osc /2 001 =f osc /8 010 =f osc /32 011 =f rc (clock supplied from a dedicated rc oscillator) 100 =f osc /4 101 =f osc /16 110 =f osc /64 111 =f rc (clock supplied from a dedicated rc oscillator) bit 3-2 unimplemented: read as ? 0 ? bit 1-0 adpref<1:0>: adc positive voltage reference configuration bits 00 =v ref is connected to v dd 01 = reserved 10 =v ref is connected to external v ref + pin (1) 11 =v ref is connected to internal fixed voltage reference (fvr) module (1) note 1: when selecting the fvr or the v ref + pin as the source of the positive reference, be aware that a minimum voltage specification exists. see section 21.0 ?electrical specifications? for details.
? 2013 microchip technology inc. preliminary ds41674b-page 113 PIC12LF1552 register 15-3: adres0h: adc result register high (adresh) adfm = 0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<9:2> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 adres<9:2> : adc result register bits upper 8 bits of 10-bit conversion result register 15-4: adres0l: adc result register low (adresl) adfm = 0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<1:0> ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 adres<1:0> : adc result register bits lower 2 bits of 10-bit conversion result bit 5-0 reserved : do not use.
PIC12LF1552 ds41674b-page 114 preliminary ? 2013 microchip technology inc. register 15-5: adres0h: adc result register high (adresh) adfm = 1 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u ? ? ? ? ? ? adres<9:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-2 reserved : do not use. bit 1-0 adres<9:8> : adc result register bits upper 2 bits of 10-bit conversion result register 15-6: adres0l: adc result register low (adresl) adfm = 1 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 adres<7:0> : adc result register bits lower 8 bits of 10-bit conversion result
? 2013 microchip technology inc. preliminary ds41674b-page 115 PIC12LF1552 15.4 adc acquisition requirements for the adc to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 15-4 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), refer to figure 15-4 . the maximum recommended impedance for analog sources is 10 k ? . as the source impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (or changed), an adc acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 15-1 may be used. this equation assumes that 1/2 lsb error is used (1,024 steps for the adc). the 1/2 lsb error is the maximum error allowed for the adc to meet its specified resolution. equation 15-1: acquisition time example t acq amplifier settling time hold capacitor charging time temperature coefficient ++ = t amp t c t coff ++ = 2s t c temperature - 25c ?? 0.05s/c ?? ?? ++ = t c c hold r ic r ss r s ++ ?? ln(1/511) ? = 10pf 1k ? 7k ? 10k ? ++ ?? ? ln(0.001957) = 1.12 = s v applied 1e tc ? rc --------- ? ?? ?? ?? v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? = v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? v chold = v applied 1e t c ? rc --------- - ? ?? ?? ?? v chold = ;[1] v chold charged to within 1/2 lsb ;[2] v chold charge response to v applied ;combining [1] and [2] the value for t c can be approximated with the following equations: solving for t c : therefore: temperature 50c and external impedance of 10k ? 5.0v v dd = assumptions: note: where n = number of bits of the adc. t acq 2s 1.12s 50c- 25c ?? 0.05 s/c ?? ?? ++ = 4.42s = note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin leakage specification.
PIC12LF1552 ds41674b-page 116 preliminary ? 2013 microchip technology inc. figure 15-4: analog input model figure 15-5: adc transfer function c pin va rs analog 5 pf v dd v t ? 0.6v v t ? 0.6v i leakage (1) r ic ? 1k sampling switch ss rss c hold = 10 pf ref- 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance various junctions r ss note 1: refer to section 21.0 ?electrical specifications? . r ss = resistance of sampling switch input pin 3ffh 3feh adc output code 3fdh 3fch 03h 02h 01h 00h full-scale 3fbh 0.5 lsb ref- zero-scale transition ref+ transition 1.5 lsb full-scale range analog input voltage
? 2013 microchip technology inc. preliminary ds41674b-page 117 PIC12LF1552 table 15-3: summary of registers associated with adc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page adcon0 ? chs<4:0> go/done adon 111 adcon1 adfm adcs<2:0> ? ? adpref<1:0> 112 adres0h adc result register high 113 , 114 adres0l adc result register low 113 , 114 ansela ? ? ansa5 ansa4 ? ansa2 ansa1 ansa0 95 fvrcon fvren fvrrdy tsen tsrng ? ?adfvr<1:0> 126 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 62 pie1 ?adie ? ? sspie ? ? ? 63 pir1 ?adif ? ? sspif ? ? ? 65 trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 94 legend: ? = unimplemented read as ? 0 ?. shaded cells are not used for adc module. note 1: unimplemented, read as ? 1 ?.
PIC12LF1552 ds41674b-page 118 preliminary ? 2013 microchip technology inc. notes:
? 2013 microchip technology inc. preliminary ds41674b-page 119 PIC12LF1552 16.0 hardware capacitive voltage divider (cvd) module the hardware capacitive voltage divider (cvd) module is a peripheral, which allows the user to perform a relative capacitance measurement on any adc channel using the internal adc sample and hold capacitance as a reference. this relative capacitance measurement can be used to implement capacitive touch or proximity sensing applications. the basic principle of cvd begins with one adc channel discharging the internal sample and hold capacitor for the adc, and charging the sensor channel to v dd . then, sets the sensor channel to input and connects the sensor channel to the internal capacitor, creating a voltage divider between the two. after the voltage settles on the two capacitors, the adc will take a sample. if charging/discharging the two capacitors in an inverted direction, then a complimen- tary cvd measurement is performed. figure 16-1 shows the waveform for two inverted cvd measure- ments, which is also known is differential cvd measurement. in a typical application, an analog-to-digital converter (adc) channel is attached to a pad on a printed circuit board (pcb), which is electrically isolated from the end user. a capacitive change is detected on the adc channel using the cvd conversion method when the end user places a finger over the pcb pad, the developer then can implement software to determine a touch or proximity. key features of this module include: ? automated double sample conversions ? two result registers ? inversion of second sample ? 7-bit pre-charge timer ? 7-bit acquisition timer ? two guard ring output drives ? adjustable sample and hold capacitor array figure 16-1: differential cvd measurement waveform note: for more information on capacitive volt- age divider sensing method refer to the application note an1478, ?mtouch tm sensing solution acquisition methods capacitive voltage divider? (ds01478). internal adc hold capacitor external capacitive sensor precharge conversion acquisition precharge conversion acquisition v dd v ss voltage time first sample second sample
PIC12LF1552 ds41674b-page 120 preliminary ? 2013 microchip technology inc. figure 16-2: hardware capacitive vo ltage divider block diagram additional sample and hold cap v dd adout adoen adc conversion bus adout pad adippol = 1 adippol = 0 addcap<2:0> (uses adc mux) v gnd anx anx pads v gnd v gnd v gnd
? 2013 microchip technology inc. preliminary ds41674b-page 121 PIC12LF1552 16.1 hardware cvd operation capacitive voltage divider is a charge averaging capacitive sensing method. the hardware cvd module will automate the process of charging, averaging between the external electrode and internal adc sam- ple and hold capacitor, and initiating the adc conver- sions. the whole process can be expanded into three stages: pre-charge, acquisition, and conversion. see figure 16-3 for basic information on the timing of three stages. 16.1.1 pre-charge timer the pre-charge stage is an optional 1-127 instruction cycle time delay used to put the external adc channel and the internal sample and hold capacitor (c hold ) into pre-conditioned states. the pre-charge stage of conversion is enabled by writing a non-zero value to the adpre<6:0> bits of the aadpre register. this stage is initiated when a conversion sequence is started by either the go/done bit or a special event trigger. when initiating an adc conversion, if the adpre bits are cleared, this stage is skipped. during the pre-charge time, c hold is connected to either v dd or v ss , depending on the value of the adippol bit of the aadcon3 register. the port pin logic of the selected analog channel is overridden to drive a digital high or low out. the output polarity of this override is determined by the adeppol bit of the aadcon3 register. when both the adoen and adooen bits of the aadcon3 register are set, the adout pin is overridden during pre-charge. see section 16.1.9 ?analog bus visibility? for more information. this override functions the same as the channel pin overrides, but the polarity is selected by the adippol bit of the aadcon3 register. see figure 16-2 . even though the analog channel of the pin is selected, the analog multiplexer is forced open during the pre- charge stage. the adc multiplexor logic is overridden and disabled only during the pre-charge time. 16.1.2 acquisition timer the acquisition timer is used to either acquire the sig- nal or to charge averaging. the acquisition delay time is from 1 to 127 instruction cycles and is used to allow the voltage on the internal sample and hold capacitor (c hold ) to charge or discharge from the selected ana- log channel. the acquisition time of conversion is enabled by writing a non-zero value to the adacq<6:0> bits of the aadacq register. when the acquisition time is enabled, the time starts immediately following the pre-charge stage. if the adpre<6:0> bits of the aadpre register are set to zero, the acquisition time is initiated by either setting the go/done bit or a special event trigger. at the start of the acquisition stage, the selected adc channel is connected to c hold . this allows charge averaging between the pre-charged channel and the c hold capacitor. 16.1.3 starting a conversion to enable the adc module, the adon bit of the aadcon0 register must be set. setting the go/ done bit of the aadcon0 register or by the special event trigger inputs will start the analog-to-digital conversion. once a conversion begins, it proceeds until complete, while the adon bit is set. if the adon bit is cleared, the conversion is halted. the go/done bit of the aadcon0 register indicates that a conversion is occurring, regardless of the starting trigger. see figure 16-3 . 16.1.4 completion of a conversion when the conversion is complete, the adc module will: ? clear the go/done bit of the aadcon0 register. ? set the adif interrupt flag bit of the pir1 register. ? update the aadresxh and aadresxl registers with new conversion results. 16.1.5 terminating a conversion if a conversion must be terminated before completion, clear the go/done bit. the aadresxh and aadresxl registers will be updated with the partially complete analog-to-digital conversion sample. incom- plete bits will match the last bit converted. the aadsate register can be used to track the status of the hardware cvd module during a conversion. note: the go/done bit should not be set in the same instruction that turns on the adc. refer to section section 16.1.10 ?hard- ware cvd double conversion proce- dure? note: a device reset forces all registers to their reset state. thus, the adc module is turned off and any pending conversion is terminated.
PIC12LF1552 ds41674b-page 122 preliminary ? 2013 microchip technology inc. 16.1.6 double sample conversion double sampling can be enabled by setting the addsen bit of the aadcon3 register. when this bit is set, two conversions are completed each time the go/ done bit is set or a special event trigger occurs. the go/done bit remains set for the duration of both conversions and is used to signal the end of the conversion. without setting the adipen bit, the double conversion will have identical charge/discharge on the internal and external capacitor for these two conversions. this is used to take fast cvd sample for fast response time or low power consumption application. while setting the adipen bit prior to a double conversion will allow the user to perform a pseudo-differential cvd measure- ment by subtracting the results from the double conver- sion. this is highly recommended for noise immunity purposes. the result of the first conversion is written to the aadres0h and aadres0l registers. the result of the second conversion starts two clock cycles after the first has completed, while the go/done bit remains set. when the adipen bit of aadcon3 is set, the value used by the adc for the adeppol, adippol, and grdpol bits are inverted. the value stored in those bit locations is unchanged. all other control signals remain unchanged from the first conversion. the result of the second conversion is stored in the aadres1h and aadres1l registers. see figure 16-4 and figure 16-5 for more information. 16.1.7 guard ring outputs the guard ring outputs consist of a pair of digital outputs from the hardware cvd module. this function is enabled by the grdaoe and grdboe bits of the aadgrd register. polarity of the output is controlled by the grdpol bit. the guard ring outputs of the adc are active at all times. the outputs are initialized at the start of the pre- charge stage to match the polarity of the grdpol bit. the guard output signal changes polarity at the start of the acquisition phase. the value stored by the grdpol bit does not change. when in double sampling mode, the guard ring output does not initialize on the second conversion. it toggles polarity at the start of the first acquisition stage and again for the second acquisition, back to the original state. for more infor- mation on the timing of the guard ring output, refer to figure 16-4 and figure 16-5 . a typical guard ring circuit is displayed in figure 16-2 . c guard represents the capacitance of the guard ring trace placed on a pcb board. the user selects values for ra and rb that will create a voltage profile on c guard , which will match the selected channel during acquisition. the purpose of the guard ring is to generate a signal in phase with the cvd sensing signal to minimize the effects of the parasitic capacitance on sensing electrodes. it also can be used as a mutual drive for mutual capacitive sensing. for more information about active guard and mutual drive, see application note an1478, ?mtouch tm sensing solution acquisition methods capacitive voltage divider? (ds01478). figure 16-3: guard ring circuit c guard r a r b adgrda adgrdb
? 2013 microchip technology inc. preliminary ds41674b-page 123 PIC12LF1552 figure 16-4: differential cvd with guard ring output waveform 16.1.8 additional sample and hold capacitor additional capacitance can be added in parallel with the sample and hold capacitor (c hold ) by setting the addcap<2:0> bits of the aadcap register. this bit connects a digitally programmable capacitance to the adc conversion bus, increasing the effective internal capacitance of the sample and hold capacitor in the adc module. this is used to improve the match between internal and external capacitance for a better sensing performance. the additional capacitance does not affect analog performance of the adc because it is not connected during conversion. see figure 16-1 . 16.1.9 analog bus visibility the adoen of the aadcon3 register can be used to connect the adc conversion bus to the adout pin. this connection can be used to monitor the state and behavior of the internal analog bus and it also can be used to improve the match between internal and external capacitance by connecting a external capacitor to increase the effective internal capacitance. the adoen bit provides the connection via a standard channel passgate. the adout pin connection can be overridden during the pre-charge stage of conversion. this function is controlled by the adooen bit, which corresponds to the override enable signal. the polarity of the override is set by the adippol bit. figure 16-5: hardware cvd sequence timing diagram guard ring output external capacitive sensor v dd v ss voltage time first sample second sample t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go/done bit holding capacitor c hold is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy - t ad aadres0h:aadres0l is loaded, adif bit is set, conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 on the following cycle: 1-127 t inst 1-127 t inst pre-charge acquisition/ sharing time time conversion time if adpre = 0 if adacq = 0 if adpre = 0 if adacq = 0 go/done bit is cleared (traditional timing of adc conversion) external and internal channels are charged/discharged external and internal channels share charge (traditional operation start) (t pre )(t acq )
PIC12LF1552 ds41674b-page 124 preliminary ? 2013 microchip technology inc. figure 16-6: double sa mple conversion sequence (addsen = 1 and adipen = 0 ) conversion clock aadresxl/h<9:0> 10th 9th 8th 7th 6th 5th 4th 3rd 2nd 10'h000 10th 9th 8th 7th 6th 5th 4th 3rd 2nd 10'h000 1-127 t inst (1) 1-127 t inst (1) t ad 2 inst 1-127 t inst (1) 1-127 t inst (1) pre-charge acquisition aadpre<6:0> aadacq<6:0> pre-charge acquisition aadpre<6:0> aadacq<6:0> t pre t acq t conv t pre t acq t conv 1st first result written to aadres0l/h second result written to aadres1l/h (2) (3) 1st adgrda adgrdb (grdpol = 0 ) internal c hold charging (adippol = 1 ) external channel charging (adeppol = 0 ) go/done adif 3'b001 3'b010 adstat<2:0> 3'b011 3'b101 3'b110 3'b111 3'b000 external channel connected to internal c hold note 1: when the conversion clock is adcrc, the pre-charge and acquisition timers are clocked by adcrc. 2: the aadres0l/h registers are set to zero during this period. 3: the aadres1l/h registers are set to zero during this period.
? 2013 microchip technology inc. preliminary ds41674b-page 125 PIC12LF1552 figure 16-7: double sa mple conversion sequence (addsen = 1 and adipen = 1 ) conversion clock aadresxl/h<9:0> 10th 9th 8th 7th 6th 5th 4th 3rd 2nd 10'h000 10th 9th 8th 7th 6th 5th 4th 3rd 2nd 10'h000 1-127 t inst (1) 1-127 t inst (1) t ad 2 inst 1-127 t inst (1) 1-127 t inst (1) pre-charge acquisition aadpre<6:0> aadacq<6:0> pre-charge acquisition aadpre<6:0> aadacq<6:0> t pre t acq t conv t pre t acq t conv 1st first result written to aadres0l/h second result written to aadres1l/h (2) (3) 1st adgrda adgrdb (grdpol = 0 ) internal c hold charging (adippol = 1 ) external channel charging (adeppol = 0 ) go/done adif 3'b001 3'b010 adstat<2:0> 3'b011 3'b101 3'b110 3'b111 3'b000 external channel connected to internal c hold note 1: when the conversion clock is adcrc, the pre-charge and acquisition timers are clocked by adcrc. 2: the aadres0l/h registers are set to zero during this period. 3: the aadres1l/h registers are set to zero during this period.
PIC12LF1552 ds41674b-page 126 preliminary ? 2013 microchip technology inc. 16.1.10 hardware cvd double conversion procedure this is an example procedure for using hardware cvd to perform a double conversion for differential cvd measurement with active guard drive. 1. configure port: ? enable pin output driver (refer to the tris register). ? configure pin output low (refer to the lat register). ? disable weak pull-up (refer to the wpu register). 2. configure the adc module: ? select an appropriate adc conversion clock for your oscillator frequency. ? configure voltage reference. ? select adc input channel. ? turn on the adc module. 3. configure the hardware cvd module: ? configure charge polarity and double conversion. ? configure pre-charge and acquisition timer. ? configure guard ring (optional). ? select additional capacitance (optional). 4. configure adc interrupt (optional): ? clear adc interrupt flag ? enable adc interrupt ? enable peripheral interrupt ? enable global interrupt (1) 5. start conversion by setting the go/done bit or by enabling the special event trigger in the addcon2 register. 6. wait for the adc conversion to complete by one of the following: ? polling the go/done bit. ? waiting for the adc interrupt (interrupts enabled). 7. read adc result: ? conversion 1 result in addres0h and addres0l ? conversion 2 result in addres1h and addres1l 8. clear the adc interrupt flag (required if interrupt is enabled). example 16-1: hardware cvd double conversion note 1: the global interrupt can be disabled if the user is attempting to wake-up from sleep and resume in-line code execution. ;this code block configures the adc ;for polling, vdd and vss references, fosc/16 ;clock and an0 input. ; ; the hardware cvd will perform an inverted ; double conversion, guard a and b drive are ; both enabled. ;conversion start & polling for completion are included. ; banksel trisa bcf trisa, ;set ra0 to output banksel lata bcf lata,0 ;ra output low banksel ansela bcf ansela,0 ;set ra0 to digital banksel wpua bcf wpua,0 ;disable pull-up on ra0 ; initialize adc and hardware cvd banksel aadcon0 movlw b'00000001 ;select channel an0 movwf aadcon0 banksel aadcon1 movlw b'11010000' ;vdd and vss vref movwf aadcon1 banksel aadcon3 movlw b'01000011' ;double and inverted movwf aadcon3 ;adout disabled banksel aadpre movlw .10 movwf aadpre ;pre-charge timer banksel aadacq movlw .10 movwf aadacq ;acquisition timer banksel aadgrd movlw b'11000000' ;guard on a and b movwf aadgrd banksel aadcap movlw b'00000000' movwf aadcap ;no additional ; capacitor banksel adcon0 bsf adcon0, go btfsc adcon0, go goto $-1 ;results of converions 1. goto $-1 ;no, test again banksel aadres0h ; movf aadres0h,w ;read upper 2 bits movwf resulthi ;store in gpr space movf aadres0l,w ;read lower 8 bits movwf resultlo ;store in gpr space ;results of converions 2. banksel aadres1h ; movf aadres1h,w ;read upper 2 bits movwf resulthi ;store in gpr space movf aadres1l,w ;read lower 8 bits movwf resultlo ;store in gpr space
? 2013 microchip technology inc. preliminary ds41674b-page 127 PIC12LF1552 16.1.11 hardware cvd register mapping the hardware cvd module is an enhanced expansion of the standard adc module as stated in section 15.0 ?analog-to-digital converter (adc) module? and is backward compatible with the other devices in this fam- ily. control of the standard adc module uses bank 1 registers, see tab le 1 6- 1 . this set of registers is mapped into bank 14 with the control registers for the hardware cvd module. although this subset of regis- ters has different names, they are identical. since the registers for the standard adc are mapped into the bank 14 address space, any changes to registers in bank 1 will be reflected in bank 14 and vice-versa. table 16-1: hardware cvd register mapping [bank 14 address] [bank 1 address] hardware cvd adc [711h] aadcon0 (1) [09dh] adcon0 (1) [712h] aadcon1 (1) [09eh] adcon1 (1) [713h] aadcon2 [09fh] adcon2 (1) [714h] aadcon3 [715h] aadstat [716h] aadpre [717h] aadacq [718h] aadgrd [719h] aadcap [71ah] aadres0l (1) [09bh] adres0l (1) [71bh] aadres0h (1) [09ch] adres0h (1) [71ch] aadres1l [71dh] aadres1h note 1: register is mapped in bank 1 and bank 14, using different names in each bank.
PIC12LF1552 ds41674b-page 128 preliminary ? 2013 microchip technology inc. 16.2 register definitions: hardware cvd control register 16-1: aadcon0: hardware cvd control register 0 (1) u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? chs<4:0> go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-2 chs<4:0>: analog channel select bits 11111 = fvr (fixed voltage reference) buffer 1 output (2) 11110 = reserved. no channel connected. 11101 = temperature indicator (3) 11100 = reserved. no channel connected. 11011 = reserved. no channel connected. 11010 =v refh (adc positive reference) 11001 = reserved. no channel connected. ? ? ? 00101 = reserved. no channel connected. 00100 =an4 00011 =an3 00010 =an2 00001 =an1 00000 =an0 bit 1 go/done : adc conversion status bit 1 = adc conversion cycle in progress. setting this bit starts an adc conversion cycle. this bit is automatically cleared by hardware when the adc conversion has completed. 0 = adc conversion completed/not in progress bit 0 adon: adc enable bit 1 = adc is enabled 0 = adc is disabled and consumes no operating current note 1: see section 16.1.11 ?hardware cvd register mapping? for more information. 2: see section 13.0 ?fixed voltage reference (fvr)? for more information. 3: see section 14.0 ?temperature indicator module? for more information.
? 2013 microchip technology inc. preliminary ds41674b-page 129 PIC12LF1552 register 16-2: aadcon1: hardware cvd control register 1 (1) r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 adfm adcs<2:0> ? ? adpref<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 adfm: adc result format select bit 1 = right justified. six most significant bits of aadresxh are set to ? 0 ? when the conversion result is loaded. 0 = left justified. six least significant bits of aadresxl are set to ? 0 ? when the conversion result is loaded. bit 6-4 adcs<2:0>: adc conversion clock select bits 111 =f rc (clock supplied from a dedicated rc oscillator) 110 =f osc /64 101 =f osc /16 100 =f osc /4 011 =f rc (clock supplied from a dedicated rc oscillator) 010 =f osc /32 001 =f osc /8 000 =f osc /2 bit 3-2 unimplemented: read as ? 0 ? bit 1-0 adpref<1:0>: adc positive voltage reference configuration bits 11 =v ref is connected to internal fixed voltage reference (fvr) module (2) 10 =v ref is connected to external v ref + pin 01 = reserved 00 =v ref is connected to v dd note 1: see section 16.1.11 ?hardware cvd register mapping? for more information. 2: when selecting the fvr or the v ref + pin as the source of the positive reference, be aware that a minimum voltage specification exists. see section 21.0 ?electrical specifications? for details.
PIC12LF1552 ds41674b-page 130 preliminary ? 2013 microchip technology inc. register 16-3: aadcon2: hardware cvd control register 2 (1) u-0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 u-0 ? trigsel<2:0> ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-4 trigsel<2:0>: adc special event trigger source selection bits 111 = reserved. auto-conversion trigger disabled. 110 = reserved. auto-conversion trigger disabled. 101 = reserved. auto-conversion trigger disabled. 100 = reserved. auto-conversion trigger disabled. 011 = tmr0 overflow 010 = reserved. auto-conversion trigger disabled. 001 = reserved. auto-conversion trigger disabled. 000 = no auto conversion trigger selection bits (2,3) bit 3-0 unimplemented: read as ? 0 ? note 1: see section 16.1.11 ?hardware cvd register mapping? for more information. 2: this is a rising edge sensitive input for all sources. 3: signal used to set the corresponding interrupt flag.
? 2013 microchip technology inc. preliminary ds41674b-page 131 PIC12LF1552 register 16-4: aadcon3: hardware cvd control register 3 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 adeppol adippol ? adoen adooen ? adipen addsen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 adeppol: external pre-charge polarity bit (1) 1 = selected channel is shorted to v ddio during pre-charge time 0 = selected channel is shorted to v ss during pre-charge time bit 6 adippol: internal pre-charge polarity bit (1) 1 =c hold is shorted to v refh during pre-charge time 0 =c hold is shorted to v refl during pre-charge time bit 5 unimplemented: read as ? 0 ? bit 4 adoen: adout output enable bit 1 = adout pin is connected to adc bus (normal passgate) 0 = no external connection to adc bus bit 3 adooen: adout override enable bit 1 = adout pin is overridden during pre-charge with internal polarity value 0 = adout pin is not overridden bit 2 unimplemented: read as ? 0 ? bit 1 adipen: adc invert polarity enable bit if addsen = 1 : 1 = the output value of the adeppol, adippol, and grdpol bits used by the adc are inverted for the second conversion 0 = the second adc conversion proceeds like the first if addsen = 0 : this bit has no effect. bit 0 addsen: adc double sample enable bit 1 = the adc immediately starts a new conversion after completing a conversion. go/done bit is not automatically clear at end of conversion 0 = adc operates in the traditional, single conversion mode note 1: when the addsen = 1 and adipen = 1 ; the polarity of this output is inverted for the second conversion time. the stored bit value does not change.
PIC12LF1552 ds41674b-page 132 preliminary ? 2013 microchip technology inc. register 16-5: aadstat: hardware cvd status register register 16-6: aadpre: hardware cvd pre-charge control register u-0 u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? ? ? ? adconv adstg<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-3 unimplemented: read as ? 0 ? bit 2 adconv: adc conversion status bit 1 = indicates adc in conversion sequence for aadres1h:aadres1l 0 = indicates adc in conversion sequence for aadres0h:aadres0l (also reads ? 0 ? when go/done = 0 ) bit 1-0 adstg<1:0>: adc stage status bit 11 = adc module is in conversion stage 10 = adc module is in acquisition stage 01 = adc module is in pre-charge stage 00 = adc module is not converting (same as go/done = 0 ) u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? adpre<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-0 adpre<6:0>: pre-charge time select bits (1) 111 1111 = pre-charge for 127 instruction cycles 111 1110 = pre-charge for 126 instruction cycles ? ? ? 000 0001 = pre-charge for 1 instruction cycle (fosc/4) 000 0000 = adc pre-charge time is disabled note 1: when the frc clock is selected as the conversion clock source, it is also the clock used for the pre-charge and acquisition times.
? 2013 microchip technology inc. preliminary ds41674b-page 133 PIC12LF1552 register 16-7: aadacq: hardware cvd ac quisition time control register register 16-8: aadgrd: hardware cv d guard ring control register u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? adacq<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-0 adacq<6:0>: acquisition/charge share time select bits (1) 111 1111 = acquisition/charge share for 127 instruction cycles 111 1110 = acquisition/charge share for 126 instruction cycles ? ? ? 000 0001 = acquisition/charge share for one instruction cycle (fosc/4) 000 0000 = adc acquisition/charge share time is disabled note 1: when the frc clock is selected as the conversion clock source, it is also the clock used for the pre-charge and acquisition times. r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 u-0 u-0 grdboe (2) grdaoe (2) grdpol (1,2) ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 grdboe: guard ring b output enable bit (2) 1 = adc guard ring output is enabled to adgrdb pin. its corresponding trisx bit must be clear. 0 = no adc guard ring function to this pin is enabled bit 6 grdaoe: guard ring a output enable bit (2) 1 = adc guard ring output is enabled to adgrda pin. its corresponding trisx, x bit must be clear. 0 = no adc guard ring function is enabled bit 5 grdpol: guard ring polarity selection bit (1,2) 1 = adc guard ring outputs start as digital high during pre-charge stage 0 = adc guard ring outputs start as digital low during pre-charge stage bit 4-0 unimplemented: read as ? 0 ? note 1: when the addsen = 1 and adipen = 1 ; the polarity of this output is inverted for the second conversion time. the stored bit value does not change. 2: guard ring outputs are maintained while adon = 1 . the adgrda output switches polarity at the start of the acquisition time.
PIC12LF1552 ds41674b-page 134 preliminary ? 2013 microchip technology inc. register 16-9: aadcap: hardware cvd additional sample capacitor selection register u-0 u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 ? addcap<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-3 unimplemented: read as ? 0 ? bit 2-0 addcap: adc additional sample capacitor selection bits 111 = nominal additional sample capacitor of 28 pf 110 = nominal additional sample capacitor of 24 pf 101 = nominal additional sample capacitor of 20 pf 100 = nominal additional sample capacitor of 16 pf 011 = nominal additional sample capacitor of 12 pf 010 = nominal additional sample capacitor of 8 pf 001 = nominal additional sample capacitor of 4 pf 000 = additional sample capacitor is disabled
? 2013 microchip technology inc. preliminary ds41674b-page 135 PIC12LF1552 register 16-10: aadresxh: hardware cvd result register msb adfm = 0 (1) r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adresx<9:2> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 ad<9:2> : most significant adc results note 1: see section 16.1.11 ?hardware cvd register mapping? for more information. register 16-11: aadresxl: hardware cv d result register lsl adfm = 0 (1) r/w-x/u r/w-x/u u-0 u-0 u-0 u-0 u-0 u-0 adresx<1:0> ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 ad<1:0> : adc result register bits lower 2 bits of 10-bit conversion result bit 5-0 reserved : do not use. note 1: see section 16.1.11 ?hardware cvd register mapping? for more information.
PIC12LF1552 ds41674b-page 136 preliminary ? 2013 microchip technology inc. register 16-12: aadresxh: hardware cvd result register msb adfm = 1 (1) u-0 u-0 u-0 u-0 u-0 u-0 r/w-x/u r/w-x/u ? ? ? ? ? ? adresx<9:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-2 reserved : do not use. bit 1-0 ad<9:8> : most significant adc results note 1: see section 16.1.11 ?hardware cvd register mapping? for more information. register 16-13: aadresxl: hardware cvd result register lsb adfm = 1 (1) r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adresx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 ad<7:0> : adc result register bits lower 2 bits of 10-bit conversion result note 1: see section 16.1.11 ?hardware cvd register mapping? for more information.
? 2013 microchip technology inc. preliminary ds41674b-page 137 PIC12LF1552 table 16-2: summary of registers associated with hardware cvd name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page aadcap ? ? ? ? ? addcap<2:0> 134 aadcon0 ?chs<4:0> go/done adon 128 aadcon1 adfm adcs<2:0> ? ? adpref<1:0> 129 aadcon2 ?trigsel<2:0> ? ? ? ? 130 aadcon3 adeppol adippol ? adoen adooen ? adipen addsen 131 aadgrd grdboe grdaoe grdpol ? ? ? ? ? 133 aadpre ? adpre<6:0> 132 aadres0h adc result 0 register high 135 aadres0l adc result 0 register low 135 aadres1h adc result 1 register high 136 aadres1l adc result 1 register low 136 aadstat ? ? ? ? ? adconv adstg<1:0> 132 aadacq ? adacq<6:0> 133 ansela ? ? ansa5 ansa4 ? ansa2 ansa1 ansa0 95 fvrcon fvren fvrrdy tsen tsrng ? ?adfvr<1:0> 102 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 62 pie1 ?adie ? ? sspie ? ? ? 63 pir1 ?adif ? ? sspif ? ? ? 65 trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 94 legend: ? = unimplemented read as ? 0 ?. shaded cells are not used for hardware cvd module. note 1: unimplemented, read as ? 1 ?.
PIC12LF1552 ds41674b-page 138 preliminary ? 2013 microchip technology inc. 17.0 timer0 module the timer0 module is an 8-bit timer/counter with the following features: ? 8-bit timer/counter register (tmr0) ? 8-bit prescaler (independent of watchdog timer) ? programmable internal or external clock source ? programmable external clock edge selection ? interrupt on overflow figure 17-1 is a block diagram of the timer0 module. 17.1 timer0 operation the timer0 module can be used as either an 8-bit timer or an 8-bit counter. 17.1.1 8-bit timer mode the timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit timer mode is selected by clearing the tmr0cs bit of the option_reg register. when tmr0 is written, the increment is inhibited for two instruction cycles immediately following the write. 17.1.2 8-bit counter mode in 8-bit counter mode, the timer0 module will increment on every rising or falling edge of the t0cki pin. 8-bit counter mode using the t0cki pin is selected by setting the tmr0cs bit in the option_reg register to ? 1 ?. the rising or falling transition of the incrementing edge for either input source is determined by the tmr0se bit in the option_reg register. figure 17-1: block diagra m of the timer0 note: the value written to the tmr0 register can be adjusted, in order to account for the two instruction cycle delay when tmr0 is written. t0cki tmr0se tmr0 ps<2:0> data bus set flag bit tmr0if on overflow tmr0cs 0 1 0 1 8 8 8-bit prescaler f osc /4 psa sync 2 t cy
? 2013 microchip technology inc. preliminary ds41674b-page 139 PIC12LF1552 17.1.3 software programmable prescaler a software programmable prescaler is available for exclusive use with timer0. the prescaler is enabled by clearing the psa bit of the option_reg register. there are eight prescaler options for the timer0 module ranging from 1:2 to 1:256. the prescale values are selectable via the ps<2:0> bits of the option_reg register. in order to have a 1:1 prescaler value for the timer0 module, the prescaler must be disabled by setting the psa bit of the option_reg register. the prescaler is not readable or writable. all instructions writing to the tmr0 register will clear the prescaler. 17.1.4 timer0 interrupt timer0 will generate an interrupt when the tmr0 register overflows from ffh to 00h. the tmr0if interrupt flag bit of the intcon register is set every time the tmr0 register overflows, regardless of whether or not the timer0 interrupt is enabled. the tmr0if bit can only be cleared in software. the timer0 interrupt enable is the tmr0ie bit of the intcon register. 17.1.5 8-bit counter mode synchronization when in 8-bit counter mode, the incrementing edge on the t0cki pin must be synchronized to the instruction clock. synchronization can be accomplished by sampling the prescaler output on the q2 and q4 cycles of the instruction clock. the high and low periods of the external clocking source must meet the timing requirements as shown in section 21.0 ?electrical specifications? . 17.1.6 operation during sleep timer0 cannot operate while the processor is in sleep mode. the contents of the tmr0 register will remain unchanged while the processor is in sleep mode. note: the watchdog timer (wdt) uses its own independent prescaler. note: the timer0 interrupt cannot wake the processor from sleep since the timer is frozen during sleep.
PIC12LF1552 ds41674b-page 140 preliminary ? 2013 microchip technology inc. 17.2 register definitions: option register table 17-1: summary of registers associated with timer0 register 17-1: option_reg: option register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 wpuen intedg tmr0cs tmr0se psa ps<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 wpuen : weak pull-up enable bit 1 = all weak pull-ups are disabled (except mclr , if it is enabled) 0 = weak pull-ups are enabled by individual wpux latch values bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of int pin 0 = interrupt on falling edge of int pin bit 5 tmr0cs: timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (f osc /4) bit 4 tmr0se: timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is not assigned to the timer0 module 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page aadcon2 trigsel<2:0> ? ? ? ? 130 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 62 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 140 tmr0 holding register for the 8-bit timer0 count 138 * trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 94 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the timer0 module. * page provides register information. note 1: unimplemented, read as ? 1 ?. 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 bit value timer0 rate
? 2013 microchip technology inc. preliminary ds41674b-page 141 PIC12LF1552 notes:
PIC12LF1552 ds41674b-page 142 preliminary ? 2013 microchip technology inc.
? 2013 microchip technology inc. preliminary ds41674b-page 143 PIC12LF1552 18.0 master synchronous serial port module 18.1 master ssp (mssp1) module overview the master synchronous serial port (mssp1) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the mssp1 module can operate in one of two modes: ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c?) the spi interface supports the following modes and features: ?master mode ? slave mode ? clock parity ? slave select synchronization (slave mode only) ? daisy-chain connection of slave devices figure 18-1 is a block diagram of the spi interface module. figure 18-1: mssp1 blo ck diagram (spi mode) note: register names, i/o pins, and bit names may use the generic designator ?x? to indicate the use of a numeral to distinguish a particular module, when required. read write data bus sspsr reg sspm<3:0> bit 0 shift clock ss control enable edge select clock select edge select 2 (ckp, cke) 4 tris bit sdo sspbuf reg sdi ss sck t osc prescaler 4, 16, 64 baud rate generator (sspadd) sdo_out sck_out
PIC12LF1552 ds41674b-page 144 preliminary ? 2013 microchip technology inc. the i 2 c interface supports the following modes and features: ?master mode ? slave mode ? byte nacking (slave mode) ? limited multi-master support ? 7-bit and 10-bit addressing ? start and stop interrupts ? interrupt masking ? clock stretching ? bus collision detection ? general call address matching ?address masking ? address hold and data hold modes ? selectable sda hold times figure 18-2 is a block diagram of the i 2 c interface module in master mode. figure 18-3 is a diagram of the i 2 c interface module in slave mode. the PIC12LF1552 has one mssp module. figure 18-2: mssp1 block diagram (i 2 c? master mode) read write sspsr start bit, stop bit, start bit detect, sspbuf internal data bus set/reset: s, p, sspstat, wcol, sspov shift clock msb lsb sda acknowledge generate (sspcon2) stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable (rcen) clock cntl clock arbitrate/bcol detect (hold off clock source) [sspm<3:0>] baud rate reset sen, pen (sspcon2) generator (sspadd) address match detect set sspif, bclif
? 2013 microchip technology inc. preliminary ds41674b-page 145 PIC12LF1552 figure 18-3: mssp1 block diagram (i 2 c? slave mode) read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) scl sda shift clock msb lsb sspmsk reg
PIC12LF1552 ds41674b-page 146 preliminary ? 2013 microchip technology inc. 18.2 spi mode overview the serial peripheral interface (spi) bus is a synchronous serial data communication bus that operates in full-duplex mode. devices communicate in a master/slave environment where the master device initiates the communication. a slave device is controlled through a chip select known as slave select. the spi bus specifies four signal connections: ? serial clock (sck) ? serial data out (sdo) ? serial data in (sdi) ? slave select (ss ) figure 18-1 shows the block diagram of the mssp1 module when operating in spi mode. the spi bus operates with a single master device and one or more slave devices. when multiple slave devices are used, an independent slave select con- nection is required from the master device to each slave device. figure 18-4 shows a typical connection between a master device and multiple slave devices. the master selects only one slave at a time. most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. with either the master or the slave device, data is always shifted out one bit at a time, with the most significant bit (msb) shifted out first. at the same time, a new least significant bit (lsb) is shifted into the same register. figure 18-5 shows a typical connection between two processors configured as master and slave devices. data is shifted out of both shift registers on the pro- grammed clock edge and latched on the opposite edge of the clock. the master device transmits information out on its sdo output pin which is connected to, and received by, the slave?s sdi input pin. the slave device transmits infor- mation out on its sdo output pin, which is connected to, and received by, the master?s sdi input pin. to begin communication, the master device first sends out the clock signal. both the master and the slave devices should be configured for the same clock polar- ity. the master device starts a transmission by sending out the msb from its shift register. the slave device reads this bit from that same line and saves it into the lsb position of its shift register. during each spi clock cycle, a full-duplex data transmission occurs. this means that while the master device is sending out the msb from its shift register (on its sdo pin) and the slave device is reading this bit and saving it as the lsb of its shift register, that the slave device is also sending out the msb from its shift register (on its sdo pin) and the master device is reading this bit and saving it as the lsb of its shift register. after 8 bits have been shifted out, the master and slave have exchanged register values. if there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. whether the data is meaningful or not (dummy data), depends on the application software. this leads to three scenarios for data transmission: ? master sends useful data and slave sends dummy data. ? master sends useful data and slave sends useful data. ? master sends dummy data and slave sends useful data. transmissions may involve any number of clock cycles. when there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own.
? 2013 microchip technology inc. preliminary ds41674b-page 147 PIC12LF1552 figure 18-4: spi master and multiple slave connection 18.2.1 spi mode registers the mssp1 module has five registers for spi mode operation. these are: ? mssp1 status register (sspstat) ? mssp1 control register 1 (sspcon1) ? mssp1 control register 3 (sspcon3) ? mssp1 data buffer register (sspbuf) ? mssp1 address register (sspadd) ? mssp1 shift register (sspsr) (not directly accessible) sspcon1 and sspstat are the control and status registers in spi mode operation. the sspcon1 register is readable and writable. the lower 6 bits of the sspstat are read-only. the upper two bits of the sspstat are read/write. in spi master mode, sspadd can be loaded with a value used in the baud rate generator. more informa- tion on the baud rate generator is available in section 18.7 ?baud rate generator? sspsr is the shift register used for shifting data in and out. sspbuf provides indirect access to the sspsr register. sspbuf is the buffer register to which data bytes are written, and from which data bytes are read. in receive operations, sspsr and sspbuf together create a buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not buffered. a write to sspbuf will write to both sspbuf and sspsr. spi master sck sdo sdi general i/o general i/o general i/o sck sdi sdo ss spi slave #1 sck sdi sdo ss spi slave #2 sck sdi sdo ss spi slave #3
PIC12LF1552 ds41674b-page 148 preliminary ? 2013 microchip technology inc. 18.2.2 spi mode operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspcon1<5:0> and sspstat<7:6>). these control bits allow the following to be specified: ? master mode (sck is the clock output) ? slave mode (sck is the clock input) ? clock polarity (idle state of sck) ? data input sample phase (middle or end of data output time) ? clock edge (output data on rising/falling edge of sck) ? clock rate (master mode only) ? slave select mode (slave mode only) to enable the serial port, ssp enable bit, sspen of the sspcon1 register, must be set. to reset or recon- figure spi mode, clear the sspen bit, re-initialize the sspconx registers and then set the sspen bit. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port func- tion, some must have their data direction bits (in the tris register) appropriately programmed as follows: ? sdi must have corresponding tris bit set ? sdo must have corresponding tris bit cleared ? sck (master mode) must have corresponding tris bit cleared ? sck (slave mode) must have corresponding tris bit set ?ss must have corresponding tris bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. the mssp1 consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr until the received data is ready. once the 8 bits of data have been received, that byte is moved to the sspbuf register. then, the buffer full detect bit, bf of the sspstat register, and the interrupt flag bit, sspif, are set. this double-buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored and the write collision detect bit wcol of the sspcon1 register, will be set. user software must clear the wcol bit to allow the following write(s) to the sspbuf register to complete successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. the buffer full bit, bf of the sspstat register, indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp1 interrupt is used to determine when the transmission/reception has completed. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. figure 18-5: spi mast er/slave connection serial input buffer (buf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm<3:0> = 00xx serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm<3:0> = 010x serial clock ss slave select general i/o (optional) = 1010
? 2013 microchip technology inc. preliminary ds41674b-page 149 PIC12LF1552 18.2.3 spi master mode the master can initiate the data transfer at any time because it controls the sck line. the master determines when the slave (processor 2, figure 18-5 ) is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be dis- abled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). the clock polarity is selected by appropriately programming the ckp bit of the sspcon1 register and the cke bit of the sspstat register. this then, would give waveforms for spi communication as shown in figure 18-6 , figure 18-8 , figure 18-9 and figure 18-10 , where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: ?f osc /4 (or t cy ) ?f osc /16 (or 4 * t cy ) ?f osc /64 (or 16 * t cy ) ? fosc/(4 * (sspadd + 1)) figure 18-6 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 18-6: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 sdi sspif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) bit 0
PIC12LF1552 ds41674b-page 150 preliminary ? 2013 microchip technology inc. 18.2.4 spi slave mode in slave mode, the data is transmitted and received as external clock pulses appear on sck. when the last bit is latched, the sspif interrupt flag bit is set. before enabling the module in spi slave mode, the clock line must match the proper idle state. the clock line can be observed by reading the sck pin. the idle state is determined by the ckp bit of the sspcon1 register. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. the shift register is clocked from the sck pin input and when a byte is received, the device will generate an interrupt. if enabled, the device will wake-up from sleep. 18.2.4.1 daisy-chain configuration the spi bus can sometimes be connected in a daisy-chain configuration. the first slave output is con- nected to the second slave input, the second slave output is connected to the third slave input, and so on. the final slave output is connected to the master input. each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. the whole chain acts as one large communication shift register. the daisy-chain feature only requires a single slave select line from the master device. figure 18-7 shows the block diagram of a typical daisy-chain connection when operating in spi mode. in a daisy-chain configuration, only the most recent byte on the bus is required by the slave. setting the boen bit of the sspcon3 register will enable writes to the sspbuf register, even if the previous byte has not been read. this allows the software to ignore data that may not apply to it. 18.2.5 slave select synchronization the slave select can also be used to synchronize communication. the slave select line is held high until the master device is ready to communicate. when the slave select line is pulled low, the slave knows that a new transmission is starting. if the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the slave select line returns to a high state. the slave is then ready to receive a new transmission when the slave select line is pulled low again. if the slave select line is not used, there is a risk that the slave will eventually become out of sync with the master. if the slave misses a bit, it will always be one bit off in future transmissions. use of the slave select line allows the slave and master to align themselves at the beginning of each transmission. the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon1<3:0> = 0100 ). when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. external pull-up/pull-down resistors may be desirable depending on the applica- tion. when the spi module resets, the bit counter is forced to ? 0 ?. this can be done by either forcing the ss pin to a high level or clearing the sspen bit. note 1: when the spi is in slave mode with ss pin control enabled (sspcon1<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: when the spi is used in slave mode with cke set; the user must enable ss pin control. 3: while operated in spi slave mode the smp bit of the sspstat register must remain clear.
? 2013 microchip technology inc. preliminary ds41674b-page 151 PIC12LF1552 figure 18-7: spi daisy-chain connection figure 18-8: slave sele ct synchronous waveform spi master sck sdo sdi general i/o sck sdi sdo ss spi slave #1 sck sdi sdo ss spi slave #2 sck sdi sdo ss spi slave #3 sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 7 sspif interrupt cke = 0 ) cke = 0 ) write to sspbuf sspsr to sspbuf ss flag bit 0 bit 7 bit 0 bit 6 sspbuf to sspsr shift register sspsr and bit count are reset
PIC12LF1552 ds41674b-page 152 preliminary ? 2013 microchip technology inc. figure 18-9: spi mode wavefo rm (slave mode with cke = 0 ) figure 18-10: spi mode waveform (slave mode with cke = 1 ) sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt cke = 0 ) cke = 0 ) write to sspbuf sspsr to sspbuf ss flag optional bit 0 detection active write collision valid sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt cke = 1 ) cke = 1 ) write to sspbuf sspsr to sspbuf ss flag not optional write collision detection active valid
? 2013 microchip technology inc. preliminary ds41674b-page 153 PIC12LF1552 18.2.6 spi operation in sleep mode in spi master mode, module clocks may be operating at a different speed than when in full-power mode; in the case of the sleep mode, all clocks are halted. special care must be taken by the user when the mssp1 clock is much faster than the system clock. in slave mode, when mssp1 interrupts are enabled, after the master completes sending data, an mssp1 interrupt will wake the controller from sleep. if an exit from sleep mode is not desired, mssp1 interrupts should be disabled. in spi master mode, when the sleep mode is selected, all module clocks are halted and the transmis- sion/reception will remain in that state until the device wakes. after the device returns to run mode, the module will resume transmitting and receiving data. in spi slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode and data to be shifted into the spi transmit/receive shift register. when all 8 bits have been received, the mssp1 interrupt flag bit will be set and if enabled, will wake the device. table 18-1: summary of registers as sociated with spi operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ansa5 ansa4 ? ansa2 ansa1 ansa0 92 apfcon ? sdosel sssel sdsel ? ? ? ? 92 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 62 pie1 ? adie ? ?sspie ? ? ? 63 pir1 ? adif ? ? sspif ? ? ? 65 sspbuf synchronous serial port receive buffer/transmit register 147 * sspcon1 wcol sspov sspen ckp sspm<3:0> 193 sspcon3 acktim pcie scie boen sdaht sbcde ahen dhen 195 sspstat smp cke d/a p s r/w ua bf 191 trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 94 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the mssp1 in spi mode. * page provides register information. note 1: unimplemented, read as ? 1 ?.
PIC12LF1552 ds41674b-page 154 preliminary ? 2013 microchip technology inc. 18.3 i 2 c mode overview the inter-integrated circuit bus (i 2 c) is a multi-master serial data communication bus. devices communicate in a master/slave environment where the master devices initiate the communication. a slave device is controlled through addressing. the i 2 c bus specifies two signal connections: ? serial clock (scl) ? serial data (sda) figure 18-2 and figure 18-3 show the block diagrams of the mssp1 module when operating in i 2 c mode. both the scl and sda connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. figure 18-11 shows a typical connection between two processors configured as master and slave devices. the i 2 c bus can operate with one or more master devices and one or more slave devices. there are four potential modes of operation for a given device: ? master transmit mode (master is transmitting data to a slave) ? master receive mode (master is receiving data from a slave) ?slave transmit mode (slave is transmitting data to a master) ? slave receive mode (slave is receiving data from the master) to begin communication, a master device starts out in master transmit mode. the master device sends out a start bit followed by the address byte of the slave it intends to communicate with. this is followed by a single read/write bit, which determines whether the master intends to transmit to or receive data from the slave device. if the requested slave exists on the bus, it will respond with an acknowledge bit, otherwise known as an ack . the master then continues in either transmit mode or receive mode and the slave continues in the comple- ment, either in receive mode or transmit mode, respectively. a start bit is indicated by a high-to-low transition of the sda line while the scl line is held high. address and data bytes are sent out, most significant bit (msb) first. the read/write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. figure 18-11: i 2 c master/ slave connection the acknowledge bit (ack ) is an active-low signal, which holds the sda line low to indicate to the transmit- ter that the slave device has received the transmitted data and is ready to receive more. the transition of a data bit is always performed while the scl line is held low. transitions that occur while the scl line is held high are used to indicate start and stop bits. if the master intends to write to the slave, then it repeat- edly sends out a byte of data, with the slave responding after each byte with an ack bit. in this example, the master device is in master transmit mode and the slave is in slave receive mode. if the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ack bit. in this exam- ple, the master device is in master receive mode and the slave is slave transmit mode. on the last byte of data communicated, the master device may end the transmission by sending a stop bit. if the master device is in receive mode, it sends the stop bit in place of the last ack bit. a stop bit is indi- cated by a low-to-high transition of the sda line while the scl line is held high. in some cases, the master may want to maintain con- trol of the bus and re-initiate another transmission. if so, the master device may send another start bit in place of the stop bit or last ack bit when it is in receive mode. the i 2 c bus specifies three message protocols; ? single message where a master writes data to a slave. ? single message where a master reads data from a slave. ? combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. master scl sda scl sda slave v dd v dd
? 2013 microchip technology inc. preliminary ds41674b-page 155 PIC12LF1552 when one device is transmitting a logical one, or letting the line float, and a second device is transmitting a log- ical zero, or holding the line low, the first device can detect that the line is not a logical one. this detection, when used on the scl line, is called clock stretching. clock stretching gives slave devices a mechanism to control the flow of data. when this detection is used on the sda line, it is called arbitration. arbitration ensures that there is only one master device communicating at any single time. 18.3.1 clock stretching when a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. an addressed slave device may hold the scl clock line low after receiving or send- ing a bit, indicating that it is not yet ready to continue. the master that is communicating with the slave will attempt to raise the scl line in order to transfer the next bit, but will detect that the clock line has not yet been released. because the scl connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 18.3.2 arbitration each master device must monitor the bus for start and stop bits. if the device detects that the bus is busy, it cannot begin a new message until the bus returns to an idle state. however, two master devices may try to initiate a trans- mission on or about the same time. when this occurs, the process of arbitration begins. each transmitter checks the level of the sda data line and compares it to the level that it expects to find. the first transmitter to observe that the two levels do not match, loses arbitra- tion, and must stop transmitting on the sda line. for example, if one transmitter holds the sda line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the sda line will be low. the first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. the first transmitter to notice this difference is the one that loses arbitration and must stop driving the sda line. if this transmitter is also a master device, it also must stop driving the scl line. it then can monitor the lines for a stop condition before trying to reissue its transmission. in the meantime, the other device that has not noticed any difference between the expected and actual levels on the sda line continues with its original transmission. it can do so without any compli- cations, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. slave transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. if two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitra- tion. when two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.
PIC12LF1552 ds41674b-page 156 preliminary ? 2013 microchip technology inc. 18.4 i 2 c mode operation all mssp1 i 2 c communication is byte oriented and shifted out msb first. six sfr registers and two interrupt flags interface the module with the pic ? microcontroller and user software. two pins, sda and scl, are exercised by the module to communicate with other external i 2 c devices. 18.4.1 byte format all communication in i 2 c is done in 9-bit segments. a byte is sent from a master to a slave or vice-versa, followed by an acknowledge bit sent back. after the 8th falling edge of the scl line, the device outputting data on the sda changes that pin to an input and reads in an acknowledge value on the next clock pulse. the clock signal, scl, is provided by the master. data is valid to change while the scl signal is low, and sampled on the rising edge of the clock. changes on the sda line while the scl line is high define special conditions on the bus, explained below. 18.4.2 definition of i 2 c terminology there is language and terminology in the description of i 2 c communication that have definitions specific to i 2 c. that word usage is defined below and may be used in the rest of this document without explanation. this table was adapted from the philips i 2 c tm specifi- cation. 18.4.3 sda and scl pins selection of any i 2 c mode with the sspen bit set, forces the scl and sda pins to be open-drain. these pins should be set by the user to inputs by setting the appropriate tris bits. 18.4.4 sda hold time the hold time of the sda pin is selected by the sdaht bit of the sspcon3 register. hold time is the time sda is held valid after the falling edge of scl. setting the sdaht bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. table 18-2: i 2 c bus terms note: data is tied to output zero when an i 2 c mode is enabled. term description transmitter the device which shifts data out onto the bus. receiver the device which shifts data in from the bus. master the device that initiates a transfer, generates clock signals and terminates a transfer. slave the device addressed by the master. multi-master a bus with more than one device that can initiate data transfers. arbitration procedure to ensure that only one master at a time controls the bus. winning arbitration ensures that the message is not corrupted. synchronization procedure to synchronize the clocks of two or more devices on the bus. idle no master is controlling the bus, and both sda and scl lines are high. active any time one or more master devices are controlling the bus. addressed slave slave device that has received a matching address and is actively being clocked by a master. matching address address byte that is clocked into a slave that matches the value stored in sspadd. write request slave receives a matching address with r/w bit clear, and is ready to clock in data. read request master sends an address byte with the r/w bit set, indicating that it wishes to clock data out of the slave. this data is the next and all following bytes until a restart or stop. clock stretching when a device on the bus hold scl low to stall communication. bus collision any time the sda line is sampled low by the module while it is out- putting and expected high state.
? 2013 microchip technology inc. preliminary ds41674b-page 157 PIC12LF1552 18.4.5 start condition the i 2 c specification defines a start condition as a transition of sda from a high to a low state while scl line is high. a start condition is always generated by the master and signifies the transition of the bus from an idle to an active state. figure 18-12 shows wave forms for start and stop conditions. a bus collision can occur on a start condition if the module samples the sda line low before asserting it low. this does not conform to the i 2 c specification that states no bus collision can occur on a start. 18.4.6 stop condition a stop condition is a transition of the sda line from low-to-high state while the scl line is high. 18.4.7 restart condition a restart is valid any time that a stop would be valid. a master can issue a restart if it wishes to hold the bus after terminating the current transfer. a restart has the same effect on the slave that a start would, resetting all slave logic and preparing it to clock in an address. the master may want to address the same or another slave. figure 18-13 shows the wave form for a restart condition. in 10-bit addressing slave mode a restart is required for the master to clock data out of the addressed slave. once a slave has been fully addressed, match- ing both high and low address bytes, the master can issue a restart and the high address byte with the r/w bit set. the slave logic will then hold the clock and prepare to clock out data. after a full match with r/w clear in 10-bit mode, a prior match flag is set and maintained. until a stop condi- tion, a high address with r/w clear, or high address match fails. 18.4.8 start/stop condition interrupt masking the scie and pcie bits of the sspcon3 register can enable the generation of an interrupt in slave modes that do not typically support this function. slave modes where interrupt on start and stop detect are already enabled, these bits will have no effect. figure 18-12: i 2 c start and stop conditions figure 18-13: i 2 c restart condition note: at least one scl low time must appear before a stop is valid, therefore, if the sda line goes low then high again while the scl line stays high, only the start condition is detected. sda scl p stop condition s start condition change of data allowed change of data allowed restart condition sr change of data allowed change of data allowed
PIC12LF1552 ds41674b-page 158 preliminary ? 2013 microchip technology inc. 18.4.9 acknowledge sequence the 9th scl pulse for any transferred byte in i 2 c is dedicated as an acknowledge. it allows receiving devices to respond back to the transmitter by pulling the sda line low. the transmitter must release control of the line during this time to shift in the response. the acknowledge (ack ) is an active-low signal, pulling the sda line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. the result of an ack is placed in the ackstat bit of the sspcon2 register. slave software, when the ahen and dhen bits are set, allow the user to set the ack value sent back to the transmitter. the ackdt bit of the sspcon2 register is set/cleared to determine the response. slave hardware will generate an ack response if the ahen and dhen bits of the sspcon3 register are clear. there are certain conditions where an ack will not be sent by the slave. if the bf bit of the sspstat register or the sspov bit of the sspcon1 register are set when a byte is received. when the module is addressed, after the 8th falling edge of scl on the bus, the acktim bit of the sspcon3 register is set. the acktim bit indicates the acknowledge time of the active bus. the acktim status bit is only active when the ahen bit or dhen bit is enabled. 18.5 i 2 c slave mode operation the mssp1 slave mode operates in one of four modes selected in the sspm bits of sspcon1 register. the modes can be divided into 7-bit and 10-bit addressing mode. 10-bit addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. modes with start and stop bit interrupts operate the same as the other modes with sspif additionally getting set upon detection of a start, restart, or stop condition. 18.5.1 slave mode addresses the sspadd register ( register 18-6 ) contains the slave mode address. the first byte received after a start or restart condition is compared against the value stored in this register. if the byte matches, the value is loaded into the sspbuf register and an inter- rupt is generated. if the value does not match, the module goes idle and no indication is given to the software that anything happened. the ssp mask register ( register 18-5 ) affects the address matching process. see section 18.5.9 ?ssp mask register? for more information. 18.5.1.1 i 2 c slave 7-bit addressing mode in 7-bit addressing mode, the lsb of the received data byte is ignored when determining if there is an address match. 18.5.1.2 i 2 c slave 10-bit addressing mode in 10-bit addressing mode, the first received byte is compared to the binary value of ?1 1 1 1 0 a9 a8 0?. a9 and a8 are the two msb of the 10-bit address and stored in bits 2 and 1 of the sspadd register. after the acknowledge of the high byte the ua bit is set and scl is held low until the user updates sspadd with the low address. the low address byte is clocked in and all 8 bits are compared to the low address value in sspadd. even if there is not an address match; sspif and ua are set, and scl is held low until sspadd is updated to receive a high byte again. when sspadd is updated the ua bit is cleared. this ensures the module is ready to receive the high address byte on the next communication. a high and low address match as a write request is required at the start of all 10-bit addressing communi- cation. a transmission can be initiated by issuing a restart once the slave is addressed, and clocking in the high address with the r/w bit set. the slave hard- ware will then acknowledge the read request and prepare to clock out data. this is only valid for a slave after it has received a complete high and low address byte match.
? 2013 microchip technology inc. preliminary ds41674b-page 159 PIC12LF1552 18.5.2 slave reception when the r/w bit of a matching received address byte is clear, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register and acknowledged. when the overflow condition exists for a received address, then not acknowledge is given. an overflow condition is defined as either bit bf of the sspstat register is set, or bit sspov of the sspcon1 register is set. the boen bit of the sspcon3 register modifies this operation. for more information see register 18-4 . an mssp1 interrupt is generated for each transferred data byte. flag bit, sspif, must be cleared by software. when the sen bit of the sspcon2 register is set, scl will be held low (clock stretch) following each received byte. the clock must be released by setting the ckp bit of the sspcon1 register, except sometimes in 10-bit mode. see section 18.2.3 ?spi master mode? for more detail. 18.5.2.1 7-bit addressing reception this section describes a standard sequence of events for the mssp1 module configured as an i 2 c slave in 7-bit addressing mode. figure 18-14 and figure 18-15 are used as visual references for this description. this is a step by step process of what typically must be done to accomplish i 2 c communication. 1. start bit detected. 2. s bit of sspstat is set; sspif is set if interrupt on start detect is enabled. 3. matching address with r/w bit clear is received. 4. the slave pulls sda low sending an ack to the master, and sets sspif bit. 5. software clears the sspif bit. 6. software reads received address from sspbuf clearing the bf flag. 7. if sen = 1 ; slave software sets ckp bit to release the scl line. 8. the master clocks out a data byte. 9. slave drives sda low sending an ack to the master, and sets sspif bit. 10. software clears sspif. 11. software reads the received byte from sspbuf clearing bf. 12. steps 8-12 are repeated for all received bytes from the master. 13. master sends stop condition, setting p bit of sspstat, and the bus goes idle. 18.5.2.2 7-bit reception with ahen and dhen slave device reception with ahen and dhen set operate the same as without these options with extra interrupts and clock stretching added after the 8th fall- ing edge of scl. these additional interrupts allow the slave software to decide whether it wants to ack the receive address or data byte, rather than the hard- ware. this functionality adds support for pmbus? that was not present on previous versions of this module. this list describes the steps that need to be taken by slave software to use these options for i 2 c communi- cation. figure 18-16 displays a module using both address and data holding. figure 18-17 includes the operation with the sen bit of the sspcon2 register set. 1. s bit of sspstat is set; sspif is set if interrupt on start detect is enabled. 2. matching address with r/w bit clear is clocked in. sspif is set and ckp cleared after the 8th falling edge of scl. 3. slave clears the sspif. 4. slave can look at the acktim bit of the sspcon3 register to determine if the sspif was after or before the ack. 5. slave reads the address value from sspbuf, clearing the bf flag. 6. slave sets ack value clocked out to the master by setting ackdt. 7. slave releases the clock by setting ckp. 8. sspif is set after an ack , not after a nack. 9. if sen = 1 the slave hardware will stretch the clock after the ack. 10. slave clears sspif. 11. sspif set and ckp cleared after 8th falling edge of scl for a received data byte. 12. slave looks at acktim bit of sspcon3 to determine the source of the interrupt. 13. slave reads the received data from sspbuf clearing bf. 14. steps 7-14 are the same for each received data byte. 15. communication is ended by either the slave sending an ack = 1 , or the master sending a stop condition. if a stop is sent and inter- rupt-on-stop detect is disabled, the slave will only know by polling the p bit of the sspstat register. note: sspif is still set after the 9th falling edge of scl even if there is no clock stretching and bf has been cleared. only if nack is sent to master is sspif not set
PIC12LF1552 ds41674b-page 160 preliminary ? 2013 microchip technology inc. figure 18-14: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving data ack receiving data ack = 1 a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspif bf sspov 12345678 12345678 12345678 9 9 9 ack is not sent. sspov set because sspbuf is still full. cleared by software first byte of data is available in sspbuf sspbuf is read sspif set on 9th falling edge of scl cleared by software p bus master sends stop condition s from slave to master
? 2013 microchip technology inc. preliminary ds41674b-page 161 PIC12LF1552 figure 18-15: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) sen sen a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl 123456789 123456789 123456789 p sspif set on 9th scl is not held ckp is written to 1 in software, ckp is written to ? 1 ? in software, ack low because falling edge of scl releasing scl ack is not sent. bus master sends ckp sspov bf sspif sspov set because sspbuf is still full. cleared by software first byte of data is available in sspbuf ack = 1 cleared by software sspbuf is read clock is held low until ckp is set to ? 1 ? releasing scl stop condition s ack ack receive address receive data receive data r/w= 0
PIC12LF1552 ds41674b-page 162 preliminary ? 2013 microchip technology inc. figure 18-16: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 1 , dhen = 1 ) receiving address receiving data received data p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl bf ckp s p 12 3 4 56 7 8 9 12345678 9 12345678 master sends stop condition s data is read from sspbuf cleared by software sspif is set on 9th falling edge of scl, after ack ckp set by software, scl is released slave software 9 acktim cleared by hardware in 9th rising edge of scl sets ackdt to not ack when dhen= 1 : ckp is cleared by hardware on 8th falling edge of scl slave software clears ackdt to ack the received byte acktim set by hardware on 8th falling edge of scl when ahen= 1 : ckp is cleared by hardware and scl is stretched address is read from ssbuf acktim set by hardware on 8th falling edge of scl ack master releases sda to slave for ack sequence no interrupt after not ack from slave ack =1 ack ackdt acktim sspif if ahen = 1 : sspif is set
? 2013 microchip technology inc. preliminary ds41674b-page 163 PIC12LF1552 figure 18-17: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 1 , dhen = 1 ) receiving address receive data receive data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspif bf ackdt ckp s p ack s 12 34 5678 9 12 3 4567 8 9 12 345 67 8 9 ack ack cleared by software acktim is cleared by hardware sspbuf can be set by software, read any time before next byte is loaded release scl on 9th rising edge of scl received address is loaded into sspbuf slave software clears ackdt to ack r/w = 0 master releases sda to slave for ack sequence the received byte when ahen = 1 ; on the 8th falling edge of scl of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of scl when dhen = 1 ; on the 8th falling edge of scl of a received data byte, ckp is cleared received data is available on sspbuf slave sends not ack ckp is not cleared if not ack p master sends stop condition no interrupt after if not ack from slave acktim
PIC12LF1552 ds41674b-page 164 preliminary ? 2013 microchip technology inc. 18.5.3 slave transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register, and an ack pulse is sent by the slave on the ninth bit. following the ack , slave hardware clears the ckp bit and the scl pin is held low (see section 18.5.6 ?clock stretching? for more detail). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspbuf register which also loads the sspsr register. then the scl pin should be released by setting the ckp bit of the sspcon1 register. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time. the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. this ack value is copied to the ackstat bit of the sspcon2 register. if ackstat is set (not ack ), then the data transfer is complete. in this case, when the not ack is latched by the slave, the slave goes idle and waits for another occurrence of the start bit. if the sda line was low (ack ), the next transmit data must be loaded into the sspbuf register. again, the scl pin must be released by setting bit ckp. an mssp1 interrupt is generated for each data transfer byte. the sspif bit must be cleared by software and the sspstat register is used to determine the status of the byte. the sspif bit is set on the falling edge of the ninth clock pulse. 18.5.3.1 slave mode bus collision a slave receives a read request and begins shifting data out on the sda line. if a bus collision is detected and the sbcde bit of the sspcon3 register is set, the bclif bit of the pirx register is set. once a bus colli- sion is detected, the slave goes idle and waits to be addressed again. user software can use the bclif bit to handle a slave bus collision. 18.5.3.2 7-bit transmission a master device can transmit a read request to a slave, and then clock data out of the slave. the list below outlines what software for a slave will need to do to accomplish a standard transmission. figure 18-18 can be used as a reference to this list. 1. master sends a start condition on sda and scl. 2. s bit of sspstat is set; sspif is set if interrupt on start detect is enabled. 3. matching address with r/w bit set is received by the slave setting sspif bit. 4. slave hardware generates an ack and sets sspif. 5. sspif bit is cleared by user. 6. software reads the received address from sspbuf, clearing bf. 7. r/w is set so ckp was automatically cleared after the ack. 8. the slave software loads the transmit data into sspbuf. 9. ckp bit is set releasing scl, allowing the master to clock the data out of the slave. 10. sspif is set after the ack response from the master is loaded into the ackstat register. 11. sspif bit is cleared. 12. the slave software checks the ackstat bit to see if the master wants to clock out more data. 13. steps 9-13 are repeated for each transmitted byte. 14. if the master sends a not ack ; the clock is not held, but sspif is still set. 15. the master sends a restart condition or a stop. 16. the slave is no longer addressed. note 1: if the master ack s the clock will be stretched. 2: ackstat is the only bit updated on the rising edge of scl (9th) rather than the falling.
? 2013 microchip technology inc. preliminary ds41674b-page 165 PIC12LF1552 figure 18-18: i 2 c slave, 7-bit address, transmission (ahen = 0 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda scl sspif bf ckp ackstat r/w d/a s p received address when r/w is set r/w is copied from the indicates an address is read from sspbuf scl is always held low after 9th scl falling edge matching address byte has been received masters not ack is copied to ackstat ckp is not held for not ack bf is automatically cleared after 8th falling edge of scl data to transmit is loaded into sspbuf set by software cleared by software ack ack ack r/w = 1 s p master sends stop condition
PIC12LF1552 ds41674b-page 166 preliminary ? 2013 microchip technology inc. 18.5.3.3 7-bit transmission with address hold enabled setting the ahen bit of the sspcon3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. once a matching address has been clocked in, ckp is cleared and the sspif interrupt is set. figure 18-19 displays a standard waveform of a 7-bit address slave transmission with ahen enabled. 1. bus starts idle. 2. master sends start condition; the s bit of sspstat is set; sspif is set if interrupt on start detect is enabled. 3. master sends matching address with r/w bit set. after the 8th falling edge of the scl line the ckp bit is cleared and sspif interrupt is gener- ated. 4. slave software clears sspif. 5. slave software reads acktim bit of sspcon3 register, and r/w and d/a of the sspstat register to determine the source of the interrupt. 6. slave reads the address value from the sspbuf register clearing the bf bit. 7. slave software decides from this information if it wishes to ack or not ack and sets the ackdt bit of the sspcon2 register accordingly. 8. slave sets the ckp bit releasing scl. 9. master clocks in the ack value from the slave. 10. slave hardware automatically clears the ckp bit and sets sspif after the ack if the r/w bit is set. 11. slave software clears sspif. 12. slave loads value to transmit to the master into sspbuf setting the bf bit. 13. slave sets ckp bit releasing the clock. 14. master clocks out the data from the slave and sends an ack value on the 9th scl pulse. 15. slave hardware copies the ack value into the ackstat bit of the sspcon2 register. 16. steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. if the master sends a not ack the slave releases the bus allowing the master to send a stop and end the communication. note: sspbuf cannot be loaded until after the ack. note: master must send a not ack on the last byte to ensure that the slave releases the scl line to receive a stop.
? 2013 microchip technology inc. preliminary ds41674b-page 167 PIC12LF1552 figure 18-19: i 2 c slave, 7-bit address, transmission (ahen = 1 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda scl sspif bf ackdt ackstat ckp r/w d/a received address is read from sspbuf bf is automatically cleared after 8th falling edge of scl data to transmit is loaded into sspbuf cleared by software slave clears ackdt to ack address master?s ack response is copied to sspstat ckp not cleared after not ack set by software, releases scl acktim is cleared on 9th rising edge of scl acktim is set on 8th falling edge of scl when ahen = 1 ; ckp is cleared by hardware after receiving matching address. when r/w = 1 ; ckp is always cleared after ack s p master sends stop condition ack r/w = 1 master releases sda to slave for ack sequence ack ack acktim
PIC12LF1552 ds41674b-page 168 preliminary ? 2013 microchip technology inc. 18.5.4 slave mode 10-bit address reception this section describes a standard sequence of events for the mssp1 module configured as an i 2 c slave in 10-bit addressing mode. figure 18-20 is used as a visual reference for this description. this is a step by step process of what must be done by slave software to accomplish i 2 c communication. 1. bus starts idle. 2. master sends start condition; s bit of sspstat is set; sspif is set if interrupt on start detect is enabled. 3. master sends matching high address with r/w bit clear; ua bit of the sspstat register is set. 4. slave sends ack and sspif is set. 5. software clears the sspif bit. 6. software reads received address from sspbuf clearing the bf flag. 7. slave loads low address into sspadd, releasing scl. 8. master sends matching low address byte to the slave; ua bit is set. 9. slave sends ack and sspif is set. 10. slave clears sspif. 11. slave reads the received matching address from sspbuf clearing bf. 12. slave loads high address into sspadd. 13. master clocks a data byte to the slave and clocks out the slaves ack on the 9th scl pulse; sspif is set. 14. if sen bit of sspcon2 is set, ckp is cleared by hardware and the clock is stretched. 15. slave clears sspif. 16. slave reads the received byte from sspbuf clearing bf. 17. if sen is set the slave sets ckp to release the scl. 18. steps 13-17 repeat for each received byte. 19. master sends stop to end the transmission. 18.5.5 10-bit addressing with address or data hold reception using 10-bit addressing with ahen or dhen set is the same as with 7-bit modes. the only difference is the need to update the sspadd register using the ua bit. all functionality, specifically when the ckp bit is cleared and scl line is held low are the same. figure 18-21 can be used as a reference of a slave in 10-bit addressing with ahen set. figure 18-22 shows a standard waveform for a slave transmitter in 10-bit addressing mode. note: updates to the sspadd register are not allowed until after the ack sequence. note: if the low address does not match, sspif and ua are still set so that the slave software can set sspadd back to the high address. bf is not set because there is no match. ckp is unaffected.
? 2013 microchip technology inc. preliminary ds41674b-page 169 PIC12LF1552 figure 18-20: i 2 c slave, 10-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) sspif receive first address byte ack receive second address byte ack receive data ack receive data ack 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl ua ckp 1 2345678 912345678 912345678 9 12345678 9 p master sends stop condition cleared by software receive address is software updates sspadd data is read scl is held low set by software, while ckp = 0 from sspbuf releasing scl when sen = 1 ; ckp is cleared after 9th falling edge of received byte read from sspbuf and releases scl when ua = 1 ; if address matches set by hardware on 9th falling edge sspadd it is loaded into sspbuf scl is held low s bf
PIC12LF1552 ds41674b-page 170 preliminary ? 2013 microchip technology inc. figure 18-21: i 2 c slave, 10-bit address, reception (sen = 0 , ahen = 1 , dhen = 0 ) receive first address byte ua receive second address byte ua receive data ack receive data 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 sda scl sspif bf ackdt ua ckp acktim 12345678 9 s ack ack 12 345678 9 12345678 91 2 sspbuf is read from received data sspbuf can be read anytime before the next received byte cleared by software falling edge of scl not allowed until 9th update to sspadd is set ckp with software releases scl scl clears ua and releases update of sspadd, set by hardware on 9th falling edge slave software clears ackdt to ack the received byte if when ahen = 1 ; on the 8th falling edge of scl of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of scl cleared by software r/w = 0
? 2013 microchip technology inc. preliminary ds41674b-page 171 PIC12LF1552 figure 18-22: i 2 c slave, 10-bit address, transmission (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving second address byte sr receive first address byte ack transmitting data byte 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 1 1 1 0 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspif bf ua ckp r/w d/a 1 2345 6789 1 2345 6789 1 23 4 5 6789 1 23456 789 ack = 1 p master sends stop condition master sends not ack master sends restart event ack r/w = 0 s cleared by software after sspadd is updated, ua is cleared and scl is released high address is loaded received address is data to transmit is set by software indicates an address when r/w = 1 ; r/w is copied from the set by hardware ua indicates sspadd sspbuf loaded with received address must be updated has been received loaded into sspbuf releases scl masters not ack is copied matching address byte ckp is cleared on 9th falling edge of scl read from sspbuf back into sspadd ackstat set by hardware
PIC12LF1552 ds41674b-page 172 preliminary ? 2013 microchip technology inc. 18.5.6 clock stretching clock stretching occurs when a device on the bus holds the scl line low, effectively pausing communi- cation. the slave may stretch the clock to allow more time to handle data or prepare a response for the mas- ter device. a master device is not concerned with stretching as anytime it is active on the bus and not transferring data, it is stretching. any stretching done by a slave is invisible to the master software and han- dled by the hardware that generates scl. the ckp bit of the sspcon1 register is used to con- trol stretching in software. any time the ckp bit is cleared, the module will wait for the scl line to go low and then hold it. setting ckp will release scl and allow more communication. 18.5.6.1 normal clock stretching following an ack if the r/w bit of sspstat is set, a read request, the slave hardware will clear ckp. this allows the slave time to update sspbuf with data to transfer to the master. if the sen bit of sspcon2 is set, the slave hardware will always stretch the clock after the ack sequence. once the slave is ready; ckp is set by software and communication resumes. 18.5.6.2 10-bit addressing mode in 10-bit addressing mode, when the ua bit is set, the clock is always stretched. this is the only time the scl is stretched without ckp being cleared. scl is released immediately after a write to sspadd. 18.5.6.3 byte nacking when ahen bit of sspcon3 is set; ckp is cleared by hardware after the 8th falling edge of scl for a received matching address byte. when dhen bit of sspcon3 is set; ckp is cleared after the 8th falling edge of scl for received data. stretching after the 8th falling edge of scl allows the slave to look at the received address or data and decide if it wants to ack the received data. 18.5.7 clock synchronization and the ckp bit any time the ckp bit is cleared, the module will wait for the scl line to go low and then hold it. however, clearing the ckp bit will not assert the scl output low until the scl output is already sampled low. there- fore, the ckp bit will not assert the scl line until an external i 2 c master device has already asserted the scl line. the scl output will remain low until the ckp bit is set and all other devices on the i 2 c bus have released scl. this ensures that a write to the ckp bit will not violate the minimum high time requirement for scl (see figure 18-23 ). figure 18-23: clock synchronization timing note 1: the bf bit has no effect on if the clock will be stretched or not. this is different than previous versions of the module that would not stretch the clock, clear ckp, if sspbuf was read before the 9th falling edge of scl. 2: previous versions of the module did not stretch the clock for a transmission if ssp- buf was loaded before the 9th falling edge of scl. it is now always cleared for read requests. note: previous versions of the module did not stretch the clock if the second address byte did not match. sda scl dx ? ? 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspcon1 ckp master device releases clock master device asserts clock
? 2013 microchip technology inc. preliminary ds41674b-page 173 PIC12LF1552 18.5.8 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually deter- mines which device will be the slave addressed by the master device. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is a reserved address in the i 2 c protocol, defined as address 0x00. when the gcen bit of the sspcon2 register is set, the slave module will automatically ack the reception of this address regardless of the value stored in sspadd. after the slave clocks in an address of all zeros with the r/w bit clear, an interrupt is generated and slave software can read sspbuf and respond. figure 18-24 shows a general call reception sequence. in 10-bit address mode, the ua bit will not be set on the reception of the general call address. the slave will prepare to receive the second byte as data, just as it would in 7-bit mode. if the ahen bit of the sspcon3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the 8th falling edge of scl. the slave must then set its ackdt value and release the clock with communication progressing as it would normally. figure 18-24: slave mode general call address sequence 18.5.9 ssp mask register an ssp mask (sspmsk) register ( register 18-5 ) is available in i 2 c slave mode as a mask for the value held in the sspsr register during an address comparison operation. a zero (? 0 ?) bit in the sspmsk register has the effect of making the corresponding bit of the received address a ?don?t care?. this register is reset to all ? 1 ?s upon any reset condition and, therefore, has no effect on standard ssp operation until written with a mask value. the ssp mask register is active during: ? 7-bit address mode: address compare of a<7:1>. ? 10-bit address mode: address compare of a<7:0> only. the ssp mask has no effect during the reception of the first (high) byte of the address. sda scl s sspif bf (sspstat<0>) cleared by software sspbuf is read r/w = 0 ack general call address address is compared to general call address receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack , set interrupt gcen (sspcon2<7>) ?1?
PIC12LF1552 ds41674b-page 174 preliminary ? 2013 microchip technology inc. 18.6 i 2 c master mode master mode is enabled by setting and clearing the appropriate sspm bits in the sspcon1 register and by setting the sspen bit. in master mode, the sda and sck pins must be configured as inputs. the mssp peripheral hardware will override the output driver tris controls when necessary to drive the pins low. master mode of operation is supported by interrupt generation on the detection of the start and stop con- ditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp1 module is disabled. con- trol of the i 2 c bus may be taken when the p bit is set, or the bus is idle. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit condition detection. start and stop condition detection is the only active circuitry in this mode. all other communication is done by the user software directly manipulating the sda and scl lines. the following events will cause the ssp interrupt flag bit, sspif, to be set (ssp interrupt, if enabled): ? start condition detected ? stop condition detected ? data transfer byte transmitted/received ? acknowledge transmitted/received ? repeated start generated 18.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ?. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address followed by a ? 1 ? to indicate the receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmit- ted. start and stop conditions indicate the beginning and end of transmission. a baud rate generator is used to set the clock frequency output on scl. see section 18.7 ?baud rate generator? for more detail. note 1: the mssp1 module, when configured in i 2 c master mode, does not allow queue- ing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to initiate transmission before the start condition is complete. in this case, the sspbuf will not be written to and the wcol bit will be set, indicating that a write to the sspbuf did not occur 2: when in master mode, start/stop detection is masked and an interrupt is generated when the sen/pen bit is cleared and the generation is complete.
? 2013 microchip technology inc. preliminary ds41674b-page 175 PIC12LF1552 18.6.2 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, releases the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<7:0> and begins count- ing. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device ( figure 18-25 ). figure 18-25: baud rate generator timing with clock arbitration 18.6.3 wcol status flag if the user writes the sspbuf when a start, restart, stop, receive or transmit sequence is in progress, the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). any time the wcol bit is set it indicates that an action on sspbuf was attempted while the module was not idle. sda scl scl deasserted but slave holds dx ? ? 1 dx brg scl is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete.
PIC12LF1552 ds41674b-page 176 preliminary ? 2013 microchip technology inc. 18.6.4 i 2 c master mode start condition timing to initiate a start condition ( figure 18-26 ), the user sets the start enable bit, sen bit of the sspcon2 register. if the sda and scl pins are sampled high, the baud rate generator is reloaded with the contents of sspadd<7:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition and causes the s bit of the sspstat1 register to be set. following this, the baud rate generator is reloaded with the contents of sspadd<7:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit of the sspcon2 register will be automatically cleared by hardware; the baud rate generator is suspended, leaving the sda line held low and the start condition is complete. figure 18-26: first start bit timing note 1: if at the beginning of the start condition, the sda and scl pins are already sampled low, or if during the start condi- tion, the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag, bclif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. 2: the philips i 2 c tm specification states that a bus collision cannot occur on a start. sda scl s t brg 1st bit 2nd bit t brg sda = 1 , at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspstat<3>) and sets sspif bit
? 2013 microchip technology inc. preliminary ds41674b-page 177 PIC12LF1552 18.6.5 i 2 c master mode repeated start condition timing a repeated start condition ( figure 18-27 ) occurs when the rsen bit of the sspcon2 register is programmed high and the master state machine is no longer active. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sda is sampled high, the scl pin will be deasserted (brought high). when scl is sampled high, the baud rate generator is reloaded and begins count- ing. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0 ) for one t brg while scl is high. scl is asserted low. following this, the rsen bit of the sspcon2 register will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit of the sspstat register will be set. the sspif bit will not be set until the baud rate generator has timed out. figure 18-27: repeat start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low-to-high. ? scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. sda scl repeated start write to sspcon2 write to sspbuf occurs here at completion of start bit, hardware clears rsen bit 1st bit s bit set by hardware t brg t brg sda = 1 , sda = 1 , scl (no change) scl = 1 occurs here t brg t brg t brg and sets sspif sr
PIC12LF1552 ds41674b-page 178 preliminary ? 2013 microchip technology inc. 18.6.6 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the sspbuf register. this action will set the buffer full flag bit, bf and allow the baud rate generator to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted. scl is held low for one baud rate generator rollover count (t brg ). data should be valid before scl is released high. when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda. this allows the slave device being addressed to respond with an ack bit during the ninth bit time if an address match occurred, or if data was received prop- erly. the status of ack is written into the ackstat bit on the rising edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the ninth clock, the sspif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf, leaving scl low and sda unchanged ( figure 18-28 ). after the write to the sspbuf, each bit of the address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the falling edge of the eighth clock, the master will release the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit of the sspcon2 register. following the falling edge of the ninth clock transmission of the address, the sspif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to float. 18.6.6.1 bf status flag in transmit mode, the bf bit of the sspstat register is set when the cpu writes to sspbuf and is cleared when all 8 bits are shifted out. 18.6.6.2 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e., sspsr is still shifting out a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). wcol must be cleared by software before the next transmission. 18.6.6.3 ackstat status flag in transmit mode, the ackstat bit of the sspcon2 register is cleared when the slave has sent an acknowledge (ack = 0 ) and is set when the slave does not acknowledge (ack = 1 ). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 18.6.6.4 typical transmit sequence: 1. the user generates a start condition by setting the sen bit of the sspcon2 register. 2. sspif is set by hardware on completion of the start. 3. sspif is cleared by software. 4. the mssp1 module will wait the required start time before any other operation takes place. 5. the user loads the sspbuf with the slave address to transmit. 6. address is shifted out the sda pin until all 8 bits are transmitted. transmission begins as soon as sspbuf is written to. 7. the mssp1 module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspcon2 register. 8. the mssp1 module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 9. the user loads the sspbuf with eight bits of data. 10. data is shifted out the sda pin until all 8 bits are transmitted. 11. the mssp1 module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspcon2 register. 12. steps 8-11 are repeated for all transmitted data bytes. 13. the user generates a stop or restart condition by setting the pen or rsen bits of the sspcon2 register. interrupt is generated once the stop/restart condition is complete.
? 2013 microchip technology inc. preliminary ds41674b-page 179 PIC12LF1552 figure 18-28: i 2 c master mode waveform (transmission, 7 or 10-bit address) sda scl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared by software service routine sspbuf is written by software from ssp interrupt after start condition, sen cleared by hardware s sspbuf written with 7-bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 start condition begins from slave, clear ackstat bit sspcon2<6> ackstat in sspcon2 = 1 cleared by software sspbuf written pen r/w cleared by software
PIC12LF1552 ds41674b-page 180 preliminary ? 2013 microchip technology inc. 18.6.7 i 2 c master mode reception master mode reception ( figure 18-29 ) is enabled by programming the receive enable bit, rcen bit of the sspcon2 register. the baud rate generator begins counting and on each rollover, the state of the scl pin changes (high-to-low/low-to-high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the con- tents of the sspsr are loaded into the sspbuf, the bf flag bit is set, the sspif flag bit is set and the baud rate generator is suspended from counting, holding scl low. the mssp1 is now in idle state awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable, acken bit of the sspcon2 register. 18.6.7.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when the sspbuf register is read. 18.6.7.2 sspov status flag in receive operation, the sspov bit is set when 8 bits are received into the sspsr and the bf flag bit is already set from a previous reception. 18.6.7.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e., sspsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). 18.6.7.4 typical receive sequence: 1. the user generates a start condition by setting the sen bit of the sspcon2 register. 2. sspif is set by hardware on completion of the start. 3. sspif is cleared by software. 4. user writes sspbuf with the slave address to transmit and the r/w bit set. 5. address is shifted out the sda pin until all 8 bits are transmitted. transmission begins as soon as sspbuf is written to. 6. the mssp1 module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspcon2 register. 7. the mssp1 module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 8. user sets the rcen bit of the sspcon2 register and the master clocks in a byte from the slave. 9. after the 8th falling edge of scl, sspif and bf are set. 10. master clears sspif and reads the received byte from sspbuf, clears bf. 11. master sets ack value sent to slave in ackdt bit of the sspcon2 register and initiates the ack by setting the acken bit. 12. masters ack is clocked out to the slave and sspif is set. 13. user clears sspif. 14. steps 8-13 are repeated for each received byte from the slave. 15. master sends a not ack or stop to end communication. note: the mssp1 module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded.
? 2013 microchip technology inc. preliminary ds41674b-page 181 PIC12LF1552 figure 18-29: i 2 c master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1 ), write to sspbuf occurs here, ack from slave master configured as a receiver by programming sspcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared by software start xmit sen = 0 sspov sda = 0 , scl = 1 while cpu (sspstat<0>) ack cleared by software cleared by software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence sspov is set because sspbuf is still full sda = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspcon2<4> to start acknowledge sequence sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition cleared by software sda = ackdt = 0 last bit is shifted into sspsr and contents are unloaded into sspbuf rcen master configured as a receiver by programming sspcon2<3> (rcen = 1 ) rcen cleared automatically ack from master sda = ackdt = 0 rcen cleared automatically
PIC12LF1552 ds41674b-page 182 preliminary ? 2013 microchip technology inc. 18.6.8 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken bit of the sspcon2 register. when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit are presented on the sda pin. if the user wishes to gen- erate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the scl pin is deasserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp1 module then goes into idle mode ( figure 18-30 ). 18.6.8.1 wcol status flag if the user writes the sspbuf when an acknowledge sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). 18.6.9 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen bit of the sspcon2 register. at the end of a receive/transmit, the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sampled low, the baud rate generator is reloaded and counts down to ? 0 ?. when the baud rate generator times out, the scl pin will be brought high and one t brg (baud rate generator rollover count) later, the sda pin will be deasserted. when the sda pin is sampled high while scl is high, the p bit of the sspstat register is set. a t brg later, the pen bit is cleared and the sspif bit is set ( figure 18-31 ). 18.6.9.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). figure 18-30: acknowledge sequen ce waveform note: t brg = one baud rate generator period. sda scl sspif set at acknowledge sequence starts here, write to sspcon2 acken automatically cleared cleared in t brg t brg the end of receive 8 acken = 1 , ackdt = 0 d0 9 sspif software sspif set at the end of acknowledge sequence cleared in software ack
? 2013 microchip technology inc. preliminary ds41674b-page 183 PIC12LF1552 figure 18-31: stop cond ition receive or transmit mode 18.6.10 sleep operation while in sleep mode, the i 2 c slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp1 interrupt is enabled). 18.6.11 effects of a reset a reset disables the mssp1 module and terminates the current transfer. 18.6.12 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp1 module is disabled. control of the i 2 c bus may be taken when the p bit of the sspstat register is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will gener- ate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be monitored for arbitration to see if the signal level is the expected output level. this check is performed by hardware with the result placed in the bclif bit. the states where arbitration can be lost are: ? address transfer ? data transfer ? a start condition ? a repeated start condition ? an acknowledge condition 18.6.13 multi -master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a ? 1 ? on sda, by letting sda float high and another master asserts a ? 0 ?. when the scl pin floats high, data should be stable. if the expected data on sda is a ? 1 ? and the data sampled on the sda pin is ? 0 ?, then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif and reset the i 2 c port to its idle state ( figure 18-32 ). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are deasserted and the sspbuf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condi- tion was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are deas- serted and the respective control bits in the sspcon2 register are cleared. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register, or the bus is idle and the s and p bits are cleared. scl sda sda asserted low before rising edge of clock write to sspcon2, set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat<4>) is set. t brg to setup stop condition ack p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set
PIC12LF1552 ds41674b-page 184 preliminary ? 2013 microchip technology inc. figure 18-32: bus collision timing for transmit and acknowledge 18.6.13.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition ( figure 18-33 ). b) scl is sampled low before sda is asserted low ( figure 18-34 ). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: ? the start condition is aborted, ? the bclif flag is set and ? the mssp1 module is reset to its idle state ( figure 18-33 ). the start condition begins with the sda and scl pins deasserted. when the sda pin is sampled high, the baud rate generator is loaded and counts down. if the scl pin is sampled low while sda is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early ( figure 18-35 ). if, however, a ? 1 ? is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to zero; if the scl pin is sampled as ? 0 ? during this time, a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high, data does not match what is driven bus collision has occurred. set bus collision interrupt (bclif) by the master. by master data changes while scl = 0 note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condi- tion at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions.
? 2013 microchip technology inc. preliminary ds41674b-page 185 PIC12LF1552 figure 18-33: bus collision during start condition (sda only) figure 18-34: bus collision d uring start condition (scl = 0 ) sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1 , scl = 1 sda = 0 , scl = 1 . bclif s sspif sda = 0 , scl = 1 . sspif and bclif are cleared by software sspif and bclif are cleared by software set bclif, start condition. set bclif. sda scl sen bus collision occurs. set bclif. scl = 0 before sda = 0 , set sen, enable start sequence if sda = 1 , scl = 1 t brg t brg sda = 0 , scl = 1 bclif s sspif interrupt cleared by software bus collision occurs. set bclif. scl = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ?
PIC12LF1552 ds41674b-page 186 preliminary ? 2013 microchip technology inc. figure 18-35: brg reset due to sda arbitration during start condition sda scl sen set s less than t brg t brg sda = 0 , scl = 1 bclif s sspif s interrupts cleared by software set sspif sda = 0 , scl = 1 , scl pulled low after brg time-out set sspif ? 0 ? sda pulled low by other master. reset brg and assert sda. set sen, enable start sequence if sda = 1 , scl = 1
? 2013 microchip technology inc. preliminary ds41674b-page 187 PIC12LF1552 18.6.13.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level (case 1). b) scl goes low before sda is asserted low, indicating that another master is attempting to transmit a data ? 1 ? (case 2). when the user releases sda and the pin is allowed to float high, the brg is loaded with sspadd and counts down to zero. the scl pin is then deasserted and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ?, figure 18-36 ). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high-to-low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high-to-low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condition, see figure 18-37 . if, at the end of the brg time-out, both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 18-36: bus collision during a repeat ed start condition (case 1) figure 18-37: bus collision during repeat ed start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0 , set bclif and release sda and scl. cleared by software ? 0 ? ? 0 ? sda scl bclif rsen s sspif interrupt cleared by software scl goes low before sda, set bclif. release sda and scl. t brg t brg ? 0 ?
PIC12LF1552 ds41674b-page 188 preliminary ? 2013 microchip technology inc. 18.6.13.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been deasserted and allowed to float high, sda is sampled low after the brg has timed out (case 1). b) after the scl pin is deasserted, scl is sampled low before sda goes high (case 2). the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd and counts down to 0. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? ( figure 18-38 ). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data ? 0 ? ( figure 18-39 ). figure 18-38: bus collision during a stop condition (case 1) figure 18-39: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif ? 0 ? ? 0 ? sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high, set bclif ? 0 ? ? 0 ?
? 2013 microchip technology inc. preliminary ds41674b-page 189 PIC12LF1552 table 18-3: summary of registers associated with i 2 c? operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page: intcon gie peie tmr0ie inte iocie tmr0if intf iocif 62 pie1 ? adie ? ?sspie ? ? ? 63 pie2 ? ? ? ?bclie ? ? ? 64 pir1 ? adif ? ? sspif ? ? ? 65 pir2 ? ? ? ?bclif ? ? ? 66 sspadd add<7:0> 196 sspbuf mssp1 receive buffer/transmit register 147 * sspcon1 wcol sspov sspen ckp sspm<3:0> 193 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 194 sspcon3 acktim pcie scie boen sdaht sbcde ahen dhen 195 sspmsk msk<7:0> 196 sspstat smp cke d/a psr/w ua bf 191 trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 94 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the mssp module in i 2 c? mode. * page provides register information. note 1: unimplemented, read as ? 1 ?.
PIC12LF1552 ds41674b-page 190 preliminary ? 2013 microchip technology inc. 18.7 baud rate generator the mssp1 module has a baud rate generator avail- able for clock generation in both i 2 c and spi master modes. the baud rate generator (brg) reload value is placed in the sspadd register ( register 18-6 ). when a write occurs to sspbuf, the baud rate generator will automatically begin counting down. once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. an internal signal ?reload? in figure 18-40 triggers the value from sspadd to be loaded into the brg counter. this occurs twice for each oscillation of the module clock line. the logic dictating when the reload signal is asserted depends on the mode the mssp1 is being operated in. table 18-4 demonstrates clock rates based on instruction cycles and the brg value loaded into sspadd. equation 18-1: figure 18-40: baud rate genera tor block diagram table 18-4: mssp1 clock rate w/brg 18.7.1 alternate pin locations this module incorporates i/o pins that can be moved to other locations with the use of the alternate pin function register, apfcon. to determine which pins can be moved and what their default locations are upon a reset, see section 11.1 ?alternate pin function? for more information. f clock f osc sspxadd 1 + ?? 4 ?? ------------------------------------------------- = note: values of 0x00, 0x01 and 0x02 are not valid for sspadd when used as a baud rate generator for i 2 c. this is an implementation limitation. f osc f cy brg value f clock (2 rollovers of brg) 32 mhz 8 mhz 13h 400 khz (1) 32 mhz 8 mhz 19h 308 khz 32 mhz 8 mhz 4fh 100 khz 16 mhz 4 mhz 09h 400 khz (1) 16 mhz 4 mhz 0ch 308 khz 16 mhz 4 mhz 27h 100 khz 4 mhz 1 mhz 09h 100 khz note 1: the i 2 c interface does not conform to the 400 khz i 2 c specification (which applies to rates greater than 100 khz) in all details, but may be used with care where higher rates are required by the application. sspm<3:0> brg down counter sspxclk f osc /2 sspadd<7:0> sspm<3:0> scl reload control reload
? 2013 microchip technology inc. preliminary ds41674b-page 191 PIC12LF1552 18.8 register definitions: mssp control register 18-1: sspstat: ssp status register r/w-0/0 r/w-0/0 r-0/0 r-0/0 r-0/0 r-0/0 r-0/0 r-0/0 smp cke d/a psr/w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 smp: spi data input sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode in i 2 c master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high speed mode (400 khz) bit 6 cke: spi clock edge select bit (spi mode only) in spi master or slave mode: 1 = transmit occurs on transition from active to idle clock state 0 = transmit occurs on transition from idle to active clock state in i 2 c ? mode only: 1 = enable input logic so that thresholds are compliant with smbus specification 0 = disable smbus specific inputs bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (i 2 c mode only. this bit is cleared when the ms sp1 module is disabled, sspen is cleared.) 1 = indicates that a stop bit has been detected last (this bit is ? 0 ? on reset) 0 = stop bit was not detected last bit 3 s: start bit (i 2 c mode only. this bit is cleared when the ms sp1 module is disabled, sspen is cleared.) 1 = indicates that a start bit has been detected last (this bit is ? 0 ? on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or not ack bit. in i 2 c slave mode: 1 = read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress or-ing this bit with sen, rsen, pen, rcen or acken will indicate if the mssp1 is in idle mode. bit 1 ua: update address bit (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated
PIC12LF1552 ds41674b-page 192 preliminary ? 2013 microchip technology inc. bit 0 bf: buffer full status bit receive (spi and i 2 c modes): 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit (i 2 c mode only): 1 = data transmit in progress (does not include the ack and stop bits), sspbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspbuf is empty register 18-1: sspstat: ssp status register (continued)
? 2013 microchip technology inc. preliminary ds41674b-page 193 PIC12LF1552 register 18-2: sspcon1: ssp control register 1 r/c/hs-0/0 r/c/hs-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 wcol sspov sspen ckp sspm<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hs = bit is set by hardware c = user cleared bit 7 wcol: write collision detect bit master mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started 0 = no collision slave mode: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit (1) in spi mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr i s lost. overflow can only occur in slave mode. in slave mode, the user must read the sspbuf, even if only transmitting data, to avoid setting overflow. in master mode, the overfl ow bit is not set since each new reception (and transmission) is initiated by writi ng to the sspbuf register (must be cleared in software). 0 = no overflow in i 2 c mode: 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a ?don?t care? in transmit mode (must be cleared in software). 0 = no overflow bit 5 sspen: synchronous serial port enable bit in both modes, when enabled, these pins must be properly configured as input or output in spi mode: 1 = enables serial port and configures sck, sdo, sdi and ss as the source of the serial port pins (2) 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and configures the sda and scl pins as the source of the serial port pins (3) 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: clock polarity select bit in spi mode: 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c slave mode: scl release control 1 = enable clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) in i 2 c master mode: unused in this mode bit 3-0 sspm<3:0>: synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = reserved 0100 = spi slave mode, clock = sck pin, ss pin control enabled 0101 = spi slave mode, clock = sck pin, ss pin control disabled, ss can be used as i/o pin 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = i 2 c master mode, clock = f osc / (4 * (sspadd+1)) (4) 1001 = reserved 1010 = spi master mode, clock = f osc /(4 * (sspadd+1)) (5) 1011 = i 2 c firmware controlled master mode (slave idle) 1100 = reserved 1101 = reserved 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled note 1: in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf r egister. 2: when enabled, these pins must be properly configured as input or output. 3: when enabled, the sda and scl pins must be configured as inputs. 4: sspadd values of 0, 1 or 2 are not supported for i 2 c mode. 5: sspadd value of ? 0 ? is not supported. use sspm = 0000 instead.
PIC12LF1552 ds41674b-page 194 preliminary ? 2013 microchip technology inc. register 18-3: sspcon2: ssp control register 2 r/w-0/0 r-0/0 r/w-0/0 r/s/hs-0/0 r/s/hs- 0/0 r/s/hs-0/0 r/s/hs-0/0 r/w/hs-0/0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hc = cleared by hardware s = user set bit 7 gcen: general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address (0x00 or 00h) is received in the sspsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (in i 2 c mode only) 1 = acknowledge was not received 0 = acknowledge was received bit 5 ackdt: acknowledge data bit (in i 2 c mode only) in receive mode: value transmitted when the user initiates an acknowledge sequence at the end of a receive 1 = not acknowledge 0 = acknowledge bit 4 acken: acknowledge sequence enable bit (in i 2 c master mode only) in master receive mode: 1 = initiate acknowledge sequence on sda and scl pins, and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (in i 2 c master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (in i 2 c master mode only) sck r elease control: 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enable bit (in i 2 c master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enable/stretch enable bit in master mode: 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle in slave mode: 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is disabled note 1: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled).
? 2013 microchip technology inc. preliminary ds41674b-page 195 PIC12LF1552 register 18-4: sspcon3: ssp control register 3 r-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 acktim pcie scie boen sdaht sbcde ahen dhen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 acktim: acknowledge time status bit (i 2 c mode only) (3) 1 = indicates the i 2 c bus is in an acknowledge sequence, set on 8 th falling edge of scl clock 0 = not an acknowledge sequence, cleared on 9 th rising edge of scl clock bit 6 pcie : stop condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of stop condition 0 = stop detection interrupts are disabled (2) bit 5 scie : start condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of start or restart conditions 0 = start detection interrupts are disabled (2) bit 4 boen: buffer overwrite enable bit in spi slave mode: (1) 1 = sspbuf updates every time that a new data byte is shifted in ignoring the bf bit 0 = if new byte is received with bf bit of the sspstat register already set, sspov bit of the sspcon1 register is set, and the buffer is not updated in i 2 c master mode and spi master mode: this bit is ignored. in i 2 c slave mode: 1 = sspbuf is updated and ack is generated for a received address/data byte, ignoring the state of the sspov bit only if the bf bit = 0 . 0 = sspbuf is only updated when sspov is clear bit 3 sdaht: sda hold time selection bit (i 2 c mode only) 1 = minimum of 300 ns hold time on sda after the falling edge of scl 0 = minimum of 100 ns hold time on sda after the falling edge of scl bit 2 sbcde: slave mode bus collision detect enable bit (i 2 c slave mode only) if on the rising edge of scl, sda is sampled low when the module is outputting a high state, the bclif bit of the pir2 register is set, and bus goes idle 1 = enable slave bus collision interrupts 0 = slave bus collision interrupts are disabled bit 1 ahen: address hold enable bit (i 2 c slave mode only) 1 = following the 8th falling edge of scl for a matching received address byte; ckp bit of the sspcon1 register will be cleared and the scl will be held low. 0 = address holding is disabled bit 0 dhen: data hold enable bit (i 2 c slave mode only) 1 = following the 8th falling edge of scl for a received data byte; slave hardware clears the ckp bit of the sspcon1 register and scl is held low. 0 = data holding is disabled note 1: for daisy-chained spi operation; allows the user to i gnore all but the last received byte. sspov is still set when a new byte is received and bf = 1 , but hardware continues to write the most recent byte to sspbuf. 2: this bit has no effect in slave modes that start and stop condition detection is explicitly listed as enabled. 3: the acktim status bit is only active when the ahen bit or dhen bit is set.
PIC12LF1552 ds41674b-page 196 preliminary ? 2013 microchip technology inc. register 18-5: sspmsk: ssp mask register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 msk<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-1 msk<7:1>: mask bits 1 = the received address bit n is compared to sspadd to detect i 2 c address match 0 = the received address bit n is not used to detect i 2 c address match bit 0 msk<0>: mask bit for i 2 c slave mode, 10-bit address i 2 c slave mode, 10-bit address (sspm<3:0> = 0111 or 1111 ): 1 = the received address bit 0 is compared to sspadd<0> to detect i 2 c address match 0 = the received address bit 0 is not used to detect i 2 c address match i 2 c slave mode, 7-bit address, the bit is ignored register 18-6: sspadd: mssp1 address and baud rate register (i 2 c mode) r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 add<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared master mode: bit 7-0 add<7:0>: baud rate clock divider bits scl pin clock period = ((add<7:0> + 1) *4)/f osc 10-bit slave mode ? most significant address byte: bit 7-3 not used: unused for most significant address byte. bit state of this register is a ?don?t care?. bit pattern sent by master is fixed by i 2 c specification and must be equal to ? 11110 ?. however, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 add<2:1>: two most significant bits of 10-bit address bit 0 not used: unused in this mode. bit state is a ?don?t care?. 10-bit slave mode ? least significant address byte: bit 7-0 add<7:0>: eight least significant bits of 10-bit address 7-bit slave mode: bit 7-1 add<7:1>: 7-bit address bit 0 not used: unused in this mode. bit state is a ?don?t care?.
? 2013 microchip technology inc. preliminary ds41674b-page 197 PIC12LF1552 19.0 in-circuit serial programming? (icsp?) icsp? programming allows customers to manufacture circuit boards with unprogrammed devices. programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. five pins are needed for icsp? programming: ? icspclk ? icspdat ?mclr /v pp ?v dd ?v ss in program/verify mode the program memory, user ids and the configuration words are programmed through serial communications. the icspdat pin is a bidirec- tional i/o used for transferring the serial data and the icspclk pin is the clock input. for more information on icsp? refer to the ? PIC12LF1552 memory program- ming specification ? (ds41642). 19.1 high-voltage programming entry mode the device is placed into high-voltage programming entry mode by holding the icspclk and icspdat pins low then raising the voltage on mclr /v pp to v ihh . 19.2 low-voltage programming entry mode the low-voltage programming entry mode allows the pic ? flash mcus to be programmed using v dd only, without high voltage. when the lvp bit of configuration words is set to ? 1 ?, the low-voltage icsp programming entry is enabled. to disable the low-voltage icsp mode, the lvp bit must be programmed to ? 0 ?. entry into the low-voltage programming entry mode requires the following steps: 1. mclr is brought to v il . 2. a 32-bit key sequence is presented on icspdat, while clocking icspclk. once the key sequence is complete, mclr must be held at v il for as long as program/verify mode is to be maintained. if low-voltage programming is enabled (lvp = 1 ), the mclr reset function is automatically enabled and cannot be disabled. see section 6.5 ?mclr? for more information. the lvp bit can only be reprogrammed to ? 0 ? by using the high-voltage programming mode. 19.3 common programming interfaces connection to a target device is typically done through an icsp? header. a commonly found connector on development tools is the rj-11 in the 6p6c (6-pin, 6-connector) configuration. see figure 19-1 . figure 19-1: icd rj-11 style connector interface another connector often found in use with the pickit? programmers is a standard 6-pin header with 0.1 inch spacing. refer to figure 19-2 . 1 2 3 4 5 6 target bottom side pc board v pp /mclr v ss icspclk v dd icspdat nc pin description* 1 = v pp /mclr 2 = v dd target 3 = v ss (ground) 4 = icspdat 5 = icspclk 6 = no connect
PIC12LF1552 ds41674b-page 198 preliminary ? 2013 microchip technology inc. figure 19-2: pickit? programme r style connector interface for additional interface recommendations, refer to your specific device programmer manual prior to pcb design. it is recommended that isolation devices be used to separate the programming pins from other circuitry. the type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. see figure 19-3 for more information. figure 19-3: typical connect ion for icsp? programming 1 2 3 4 5 6 * the 6-pin header (0.100" spacing) accepts 0.025" square pins. pin description* 1 = v pp /mclr 2 = v dd target 3 = v ss (ground) 4 = icspdat 5 = icspclk 6 = no connect pin 1 indicator v dd v pp v ss external device to be data clock v dd mclr /v pp v ss icspdat icspclk * * * to normal connections * isolation devices (as required). programming signals programmed v dd
? 2013 microchip technology inc. preliminary ds41674b-page 199 PIC12LF1552 20.0 instruction set summary each instruction is a 14-bit word containing the opera- tion code (opcode) and all required operands. the opcodes are broken into three broad categories. ? byte oriented ? bit oriented ? literal and control the literal and control category contains the most var- ied instruction word format. table 20-3 lists the instructions recognized by the mpasm tm assembler. all instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: ? subroutine takes two cycles ( call , callw ) ? returns from interrupts or subroutines take two cycles ( return , retlw , retfie ) ? program branching takes two cycles ( goto , bra , brw , btfss , btfsc , decfsz , incsfz ) ? one additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. one instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 mhz, this gives a nominal instruction execution rate of 1 mhz. all instruction examples use the format ? 0xhh ? to represent a hexadecimal number, where ? h ? signifies a hexadecimal digit. 20.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified, and the result is stored according to either the instruc- tion, or the destination designator ?d?. a read operation is performed on a register even if the instruction writes to that register. table 20-1: opcode field descriptions table 20-2: abbreviation descriptions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w , d = 1 : store result in file register f. default is d = 1. n fsr or indf number. (0-1) mm pre-post increment-decrement mode selection field description pc program counter to time-out bit c carry bit dc digit carry bit z zero bit pd power-down bit
PIC12LF1552 ds41674b-page 200 preliminary ? 2013 microchip technology inc. figure 20-1: general format for instructions byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only movlp instruction only 13 5 4 0 opcode k (literal) k = 5-bit immediate value movlb instruction only 13 9 8 0 opcode k (literal) k = 9-bit immediate value bra instruction only fsr offset instructions 13 7 6 5 0 opcode n k (literal) n = appropriate fsr fsr increment instructions 13 7 6 0 opcode k (literal) k = 7-bit immediate value 13 3 2 1 0 opcode n m (mode) n = appropriate fsr m = 2-bit mode value k = 6-bit immediate value 13 0 opcode opcode only
? 2013 microchip technology inc. preliminary ds41674b-page 201 PIC12LF1552 table 20-3: PIC12LF1552 instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf addwfc andwf asrf lslf lsrf clrf clrw comf decf incf iorwf movf movwf rlf rrf subwf subwfb swapf xorwf f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d add w and f add with carry w and f and w with f arithmetic right shift logical left shift logical right shift clear f clear w complement f decrement f increment f inclusive or w with f move f move w to f rotate left f through carry rotate right f through carry subtract w from f subtract with borrow w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z c, dc, z z c, z c, z c, z z z z z z z z c c c, dc, z c, dc, z z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 byte oriented skip operations decfsz incfsz f, d f, d decrement f, skip if 0 increment f, skip if 0 1(2) 1(2) 00 00 1011 1111 dfff dfff ffff ffff 1, 2 1, 2 bit-oriented file register operations bcf bsf f, b f, b bit clear f bit set f 1 1 01 01 00bb 01bb bfff bfff ffff ffff 2 2 bit-oriented skip operations btfsc btfss f, b f, b bit test f, skip if clear bit test f, skip if set 1 (2) 1 (2) 01 01 10bb 11bb bfff bfff ffff ffff 1, 2 1, 2 literal operations addlw andlw iorlw movlb movlp movlw sublw xorlw k k k k k k k k add literal and w and literal with w inclusive or literal with w move literal to bsr move literal to pclath move literal to w subtract w from literal exclusive or literal with w 1 1 1 1 1 1 1 1 11 11 11 00 11 11 11 11 1110 1001 1000 0000 0001 0000 1100 1010 kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z z z c, dc, z z note 1: if the program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 2: if this instruction addresses an indf register and the msb of the corresponding fsr is set, this instruction will require one additional instruction cycle.
PIC12LF1552 ds41674b-page 202 preliminary ? 2013 microchip technology inc. table 20-3: PIC12LF1552 instruction set (continued) mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb control operations bra brw call callw goto retfie retlw return k ? k ? k k k ? relative branch relative branch with w call subroutine call subroutine with w go to address return from interrupt return with literal in w return from subroutine 2 2 2 2 2 2 2 2 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 inherent operations clrwdt nop option reset sleep tris ? ? ? ? ? f clear watchdog timer no operation load option_reg register with w software device reset go into standby mode load tris register with w 1 1 1 1 1 1 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 0000 0010 0001 0011 0fff to , pd to , pd c-compiler optimized addfsr moviw movwi n, k n mm k[n] n mm k[n] add literal k to fsrn move indirect fsrn to w with pre/post inc/dec modifier, mm move indfn to w, indexed indirect. move w to indirect fsrn with pre/post inc/dec modifier, mm move w to indfn, indexed indirect. 1 1 1 1 1 11 00 11 00 11 0001 0000 1111 0000 1111 0nkk 0001 0nkk 0001 1nkk kkkk 0nmm kkkk 1nmm kkkk z z 2, 3 2 2, 3 2 note 1: if the program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 2: if this instruction addresses an indf register and the msb of the corresponding fsr is set, this instruction will require one additional instruction cycle. 3: see table in the moviw and movwi instruction descriptions.
? 2013 microchip technology inc. preliminary ds41674b-page 203 PIC12LF1552 20.2 instruction descriptions addfsr add literal to fsrn syntax: [ label ] addfsr fsrn, k operands: -32 ? k ? 31 n ? [ 0, 1] operation: fsr(n) + k ? fsr(n) status affected: none description: the signed 6-bit literal ?k? is added to the contents of the fsrnh:fsrnl register pair. fsrn is limited to the range 0000h-ffffh. moving beyond these bounds will cause the fsr to wrap-around. addlw add literal and w syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (w) + k ? (w) status affected: c, dc, z description: the contents of the w register are added to the eight-bit literal ?k? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) + (f) ? (destination) status affected: c, dc, z description: add the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. addwfc add w and carry bit to f syntax: [ label ] addwfc f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (w) + (f) + (c) ? dest status affected: c, dc, z description: add w, the carry flag and data mem- ory location ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in data memory location ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w) .and. (k) ? (w) status affected: z description: the contents of w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) .and. (f) ? (destination) status affected: z description: and the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. asrf arithmetic right shift syntax: [ label ] asrf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (f<7>) ? dest<7> (f<7:1>) ? dest<6:0>, (f<0>) ? c, status affected: c, z description: the contents of register ?f? are shifted one bit to the right through the carry flag. the msb remains unchanged. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. register f c
PIC12LF1552 ds41674b-page 204 preliminary ? 2013 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 0 ? (f) status affected: none description: bit ?b? in register ?f? is cleared. bra relative branch syntax: [ label ] bra label [ label ] bra $+k operands: -256 ? label - pc + 1 ? 255 -256 ? k ? 255 operation: (pc) + 1 + k ? pc status affected: none description: add the signed 9-bit literal ?k? to the pc. since the pc will have incre- mented to fetch the next instruction, the new address will be pc + 1 + k. this instruction is a two-cycle instruc- tion. this branch has a limited range. brw relative branch with w syntax: [ label ] brw operands: none operation: (pc) + (w) ? pc status affected: none description: add the contents of w (unsigned) to the pc. since the pc will have incre- mented to fetch the next instruction, the new address will be pc + 1 + (w). this instruction is a two-cycle instruc- tion. bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 1 ? (f) status affected: none description: bit ?b? in register ?f? is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, the next instruction is executed. if bit ?b?, in register ?f?, is ? 0 ?, the next instruction is discarded, and a nop is executed instead, making this a 2-cycle instruction. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 127 0 ? b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, the next instruction is executed. if bit ?b? is ? 1 ?, then the next instruction is discarded and a nop is executed instead, making this a 2-cycle instruction.
? 2013 microchip technology inc. preliminary ds41674b-page 205 PIC12LF1552 call call subroutine syntax: [ label ] call k operands: 0 ? k ? 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<6:3>) ? pc<14:11> status affected: none description: call subroutine. first, return address (pc + 1) is pushed onto the stack. the eleven-bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruc- tion. callw subroutine call with w syntax: [ label ] callw operands: none operation: (pc) +1 ? tos, (w) ? pc<7:0>, (pclath<6:0>) ?? pc<14:8> status affected: none description: subroutine call with w. first, the return address (pc + 1) is pushed onto the return stack. then, the contents of w is loaded into pc<7:0>, and the contents of pclath into pc<14:8>. callw is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 127 operation: 00h ? (f) 1 ? z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd description: clrwdt instruction resets the watch- dog timer. it also resets the prescaler of the wdt. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f ) ? (destination) status affected: z description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
PIC12LF1552 ds41674b-page 206 preliminary ? 2013 microchip technology inc. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none description: the contents of register ?f? are decre- mented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, then a nop is executed instead, making it a 2-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 2047 operation: k ? pc<10:0> pclath<6:3> ? pc<14:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two-cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination) status affected: z description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination), skip if result = 0 status affected: none description: the contents of register ?f? are incre- mented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, a nop is executed instead, making it a 2-cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .or. (f) ? (destination) status affected: z description: inclusive or the w register with register ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?.
? 2013 microchip technology inc. preliminary ds41674b-page 207 PIC12LF1552 lslf logical left shift syntax: [ label ] lslf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (f<7>) ? c (f<6:0>) ? dest<7:1> 0 ? dest<0> status affected: c, z description: the contents of register ?f? are shifted one bit to the left through the carry flag. a ? 0 ? is shifted into the lsb. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. lsrf logical right shift syntax: [ label ] lsrf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: 0 ? dest<7> (f<7:1>) ? dest<6:0>, (f<0>) ? c, status affected: c, z description: the contents of register ?f? are shifted one bit to the right through the carry flag. a ? 0 ? is shifted into the msb. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. register f 0 c register f c 0 movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) ? (dest) status affected: z description: the contents of register f is moved to a destination dependent upon the status of d. if d = 0 ,destination is w register. if d = 1 , the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w = value in fsr register z= 1
PIC12LF1552 ds41674b-page 208 preliminary ? 2013 microchip technology inc. moviw move indfn to w syntax: [ label ] moviw ++fsrn [ label ] moviw --fsrn [ label ] moviw fsrn++ [ label ] moviw fsrn-- [ label ] moviw k[fsrn] operands: n ? [ 0 , 1 ] mm ? [ 00 , 01 , 10 , 11 ] -32 ? k ? 31 operation: indfn ? w effective address is determined by ? fsr + 1 (preincrement) ? fsr - 1 (predecrement) ? fsr + k (relative offset) after the move, the fsr value will be either: ? fsr + 1 (all increments) ? fsr - 1 (all decrements) ? unchanged status affected: z mode syntax mm preincrement ++fsrn 00 predecrement --fsrn 01 postincrement fsrn++ 10 postdecrement fsrn-- 11 description: this instruction is used to move data between w and one of the indirect registers (indfn). before/after this move, the pointer (fsrn) is updated by pre/post incrementing/decrementing it. note: the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the fsrn. fsrn is limited to the range 0000h-ffffh. incrementing/decrementing it beyond these bounds will cause it to wrap-around. movlb move literal to bsr syntax: [ label ] movlb k operands: 0 ? k ? 15 operation: k ? bsr status affected: none description: the five-bit literal ?k? is loaded into the bank select register (bsr). movlp move literal to pclath syntax: [ label ] movlp k operands: 0 ? k ? 127 operation: k ? pclath status affected: none description: the seven-bit literal ?k? is loaded into the pclath register. movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none description: the eight-bit literal ?k? is loaded into w register. the ?don?t cares? will assemble as ? 0 ?s. words: 1 cycles: 1 example: movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 127 operation: (w) ? (f) status affected: none description: move data from w register to register ?f?. words: 1 cycles: 1 example: movwf option_reg before instruction option_reg = 0xff w = 0x4f after instruction option_reg = 0x4f w = 0x4f
? 2013 microchip technology inc. preliminary ds41674b-page 209 PIC12LF1552 movwi move w to indfn syntax: [ label ] movwi ++fsrn [ label ] movwi --fsrn [ label ] movwi fsrn++ [ label ] movwi fsrn-- [ label ] movwi k[fsrn] operands: n ? [ 0 , 1 ] mm ? [ 00 , 01 , 10 , 11 ] -32 ? k ? 31 operation: w ? indfn effective address is determined by ? fsr + 1 (preincrement) ? fsr - 1 (predecrement) ? fsr + k (relative offset) after the move, the fsr value will be either: ? fsr + 1 (all increments) ? fsr - 1 (all decrements) unchanged status affected: none mode syntax mm preincrement ++fsrn 00 predecrement --fsrn 01 postincrement fsrn++ 10 postdecrement fsrn-- 11 description: this instruction is used to move data between w and one of the indirect registers (indfn). before/after this move, the pointer (fsrn) is updated by pre/post incrementing/decrementing it. note: the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the fsrn. fsrn is limited to the range 0000h-ffffh. incrementing/decrementing it beyond these bounds will cause it to wrap-around. the increment/decrement operation on fsrn will not affect any status bits. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation words: 1 cycles: 1 example: nop option load option_reg register with w syntax: [ label ] option operands: none operation: (w) ? option_reg status affected: none description: move data from w register to option_reg register. reset software reset syntax: [ label ] reset operands: none operation: execute a device reset. resets the ri flag of the pcon register. status affected: none description: this instruction provides a way to execute a hardware reset by software.
PIC12LF1552 ds41674b-page 210 preliminary ? 2013 microchip technology inc. retfie return from interrupt syntax: [ label ] retfie k operands: none operation: tos ? pc, 1 ? gie status affected: none description: return from interrupt. stack is poped and top-of-stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie (intcon<7>). this is a two-cycle instruction. words: 1 cycles: 2 example: retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the eight bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. words: 1 cycles: 2 example: table call table;w contains table ;offset value ? ;w now has table value ? ? addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; ? ? ? retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c=0 after instruction reg1 = 1110 0110 w = 1100 1100 c=1 register f c
? 2013 microchip technology inc. preliminary ds41674b-page 211 PIC12LF1552 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. sleep enter sleep mode syntax: [ label ]sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. register f c sublw subtract w from literal syntax: [ label ]sublw k operands: 0 ?? k ?? 255 operation: k - (w) ??? w) status affected: c, dc, z description: the w register is subtracted (2?s complement method) from the eight-bit literal ?k?. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ?? f ?? 127 d ? [ 0 , 1 ] operation: (f) - (w) ??? destination) status affected: c, dc, z description: subtract (2?s complement method) w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f. subwfb subtract w from f with borrow syntax: subwfb f {,d} operands: 0 ? f ? 127 d ? [0,1] operation: (f) ? (w) ? (b ) ?? dest status affected: c, dc, z description: subtract w and the borrow flag (carry) from register ?f? (2?s comple- ment method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. c = 0 w ? k c = 1 w ? k dc = 0 w<3:0> ? k<3:0> dc = 1 w<3:0> ? k<3:0> c = 0 w ? f c = 1 w ? f dc = 0 w<3:0> ? f<3:0> dc = 1 w<3:0> ? f<3:0>
PIC12LF1552 ds41674b-page 212 preliminary ? 2013 microchip technology inc. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none description: the upper and lower nibbles of regis- ter ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in register ?f?. tris load tris register with w syntax: [ label ] tris f operands: 5 ? f ? 7 operation: (w) ? tris register ?f? status affected: none description: move data from w register to tris register. when ?f? = 5, trisa is loaded. when ?f? = 6, trisb is loaded. when ?f? = 7, trisc is loaded. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .xor. (f) ??? destination) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2013 microchip technology inc. preliminary ds41674b-page 213 PIC12LF1552 21.0 electrical specifications absolute maximum ratings (?) ambient temperature under bias................................................................................................. ...... -40c to +125c storage temperature ............................................................................................................ ............ -65c to +150c voltage on v dd with respect to v ss ................................................................................................... -0.3v to +4.0v voltage on mclr with respect to vss ................................................................................................. -0.3v to +9.0v voltage on all other pins with respect to v ss ........................................................................... -0.3v to (v dd + 0.3v) total power dissipation (1) ............................................................................................................................... 800 mw maximum current out of v ss pin, -40c ? t a ? +85c for industrial............................................................... 210 ma maximum current out of v ss pin, -40c ? t a ? +125c for extended .............................................................. 95 ma maximum current into v dd pin, -40c ? t a ? +85c for industrial.................................................................. 150 ma maximum current into v dd pin, -40c ? t a ? +125c for extended ................................................................. 70 ma clamp current, i k (v pin < 0 or v pin > v dd ) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????? 20 ma maximum output current sunk by any i/o pin..................................................................................... ............... 25 ma maximum output current sourced by any i/o pin .................................................................................. ............ 25 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd ? ? i oh } + ? {(v dd ? v oh ) x i oh } + ? (v o l x i ol ). figure 21-1: PIC12LF1552 volt age frequency graph, -40c ? t a ?? +125c ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure above maximum rating conditions for extended periods may affect device reliability. note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: refer to table 21-1 for each oscillator mode?s supported frequencies. 1.8 2.5 frequency (mhz) v dd (v) 424 3.6 81216 32 28 20
PIC12LF1552 ds41674b-page 214 preliminary ? 2013 microchip technology inc. 21.1 dc characteristics: PIC12LF1552-i/e (industrial, extended) PIC12LF1552 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param. no. sym. characteristic min. typ? max. units conditions d001 v dd supply voltage (v ddmin , v ddmax ) 1.8 2.5 ? ? 3.6 3.6 v v f osc ? 16 mhz: f osc ? 32 mhz d002* v dr ram data retention voltage (1) 1.5 ? ? v device in sleep mode d002a* v por * power-on reset release voltage ?1.6? v d002b* v porr * power-on reset rearm voltage ?0.8? v d003 v adfvr fixed voltage reference voltage for adc, initial accuracy -7 -8 -7 -8 ? ? ? ? 6 6 6 6 % 1.024v, v dd ? 2.5v, 85c ( note 2 ) 1.024v, v dd ? 2.5v, 125c ( note 2 ) 2.048v, v dd ? 2.5v, 85c 2.048v, v dd ? 2.5v, 125c d003c* tcv fvr temperature coefficient, fixed voltage reference ? -130 ? ppm/c d003d* ? v fvr / ? v in line regulation, fixed voltage reference ? 0.270 ? %/v d004* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section 6.1 ?power-on reset (por)? for details. * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: for proper operation, the minimum value of the adc positive voltage reference must be 1.8v or greater. when selecting the fvr or the v ref + pin as the source of the adc positive voltage reference, be aware that the voltage must be 1.8v or greater.
? 2013 microchip technology inc. preliminary ds41674b-page 215 PIC12LF1552 figure 21-2: por and por rearm with slow rising v dd v dd v por v porr v ss v ss npor t por (3) por rearm note 1: when npor is low, the device is held in reset. 2: t por 1 ? s typical. 3: t vlow 2.7 ? s typical. t vlow (2)
PIC12LF1552 ds41674b-page 216 preliminary ? 2013 microchip technology inc. 21.2 dc characteristics: PIC12LF1552-i/e (industrial, extended) PIC12LF1552 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. units conditions v dd note supply current (i dd ) (1, 2) d010 ? 3 18 ? a1.8f osc = 31 khz lfintosc mode ?5 20 ? a3.0 d011 ? 0.4 0.70 ma 1.8 f osc = 8 mhz hfintosc mode ? 0.6 1.10 ma 3.0 d012 ? 0.6 1.2 ma 1.8 f osc = 16 mhz hfintosc mode ? 0.9 1.75 ma 3.0 d013 ? 1.6 3.5 ma 3.0 f osc = 32 mhz hfintosc mode with pll d014 ? 6 17 ? a1.8f osc = 32 khz ecl mode ?8 20 ? a3.0 d015 ? 15 165 ? a1.8f osc = 500 khz ecl mode ? 25 190 ? a3.0 d016 ? 35 170 ? a1.8f osc = 1 mhz ecm mode ? 60 250 ? a3.0 d017 ? 95 250 ? a1.8f osc = 4 mhz ecm mode ? 165 420 ? a3.0 d018 ? 0.80 ? ma 3.0 f osc = 20 mhz ech mode ? data in ?typ? column is at 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: clkin = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption.
? 2013 microchip technology inc. preliminary ds41674b-page 217 PIC12LF1552 21.3 dc characteristics: PIC12LF1552-i/e (power-down) PIC12LF1552 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. +85c max. +125c units conditions v dd note power-down base current (i pd ) (2) d020 ? 0.02 1.0 4.0 ? a 1.8 wdt, bor, fvr, and t1osc disabled, all peripherals inactive ? 0.03 1.1 4.8 ? a3.0 d021 ? 0.3 1.5 10.5 ? a 1.8 lpwdt current (note 1) ?0.52.0 16 ? a3.0 d022 ? 13 25 35 ? a 1.8 fvr current (note 1) ?22 27 37 ? a3.0 d023 ? 8 15 20 ? a 3.0 bor current (note 1) d024 ? 0.2 5 7 ? a 3.0 lpbor current d025 ? 0.03 3.5 4.0 ? a 1.8 adc current (note 1, note 3) , no conversion in progress ? 0.04 4.0 4.5 ? a3.0 d026* ? 250 ? ? ? a 1.8 adc current (note 1, note 3) , conversion in progress ?250 ? ? ? a3.0 * these parameters are characterized but not tested. ? data in ?typ? column is at 25c unless otherwise stat ed. these parameters are for design guidance only and are not tested. note 1: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . 3: adc oscillator source is f rc .
PIC12LF1552 ds41674b-page 218 preliminary ? 2013 microchip technology inc. 21.4 dc characteristics: PIC12LF1552-i/e dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym. characteristic min. typ? max. units conditions v il input low voltage i/o port: d030 with ttl buffer ? ? 0.15 v dd v1.8v ? v dd ? 3.6v d031 with schmitt trigger buffer ? ? 0.2 v dd v2.0v ? v dd ? 3.6v d032 mclr ??0.2v dd v v ih input high voltage i/o ports: ? ? d040 with ttl buffer 0.25 v dd + 0.8 ??v1.8v ? v dd ?? 3.6v d041 with schmitt trigger buffer 0.8 v dd ??v2.0v ? v dd ? 3.6v d042 mclr 0.8 v dd ??v i il input leakage current (1) d060 i/o ports ? 5 5 125 1000 na na v ss ? v pin ? v dd , pin at high- impedance at 85c 125c d061 mclr (2) ? 50 200nav ss ? v pin ? v dd at 85c i pur weak pull-up current d070* 25 100 200 ? av dd = 3.3v, v pin = v ss v ol output low voltage (3) d080 i/o ports ??0.6v i ol = 6ma, v dd = 3.3v i ol = 1.8ma, v dd = 1.8v v oh output high voltage (3) d090 i/o ports v dd - 0.7 ? ? v i oh = 3ma, v dd = 3.3v i oh = 1ma, v dd = 1.8v capacitive loading specs on output pins d101a* c io all i/o pins ? ? 50 pf * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: negative current is defined as current sourced by the pin. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: including osc2 in clkout mode.
? 2013 microchip technology inc. preliminary ds41674b-page 219 PIC12LF1552 21.5 memory programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions program memory programming specifications d110 v ihh voltage on mclr /v pp pin 8.0 ? 9.0 v (note 2) d111 i ddp supply current during programming ? ? 10 ma d112 v be v dd for bulk erase 2.7 ? v ddmax v d113 v pew v dd for write or row erase v ddmin ? v ddmax v d114 i pppgm current on mclr /v pp during erase/ write ??1.0ma d115 i ddpgm current on v dd during erase/write ? ? 5.0 ma program flash memory d121 e p cell endurance 10k ? ? e/w -40 ? c to +85 ? c (note 1) d122 v prw v dd for read/write v ddmin ? v ddmax v d123 t iw self-timed write cycle time ? 2 2.5 ms d124 t retd characteristic retention ? 40 ? year provided no other specifications are violated d125 e hefc high-endurance flash cell 100k ? ? e/w 0 ? c to +60 ? c, lower byte, last 128 addresses in flash memory ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: self-write and block erase. 2: required only if single-suppl y programming is disabled.
PIC12LF1552 ds41674b-page 220 preliminary ? 2013 microchip technology inc. 21.6 thermal considerations standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic typ. units conditions th01 ? ja thermal resistance junction to ambient 89.3 ? c/w 8-pin pdip package 149.5 ? c/w 8-pin soic package 211 ? c/w 8-pin msop package 56.7 ? c/w 8-pin dfn 3x3mm package 68 ? c/w 8-pin dfn 2x3mm package th02 ? jc thermal resistance junction to case 43.1 ? c/w 8-pin pdip package 39.9 ? c/w 8-pin soic package 39 ? c/w 8-pin msop package 9 ? c/w 8-pin dfn 3x3mm package 12.7 ? c/w 8-pin dfn 2x3mm package th03 t jmax maximum junction temperature 150 ? c th04 pd power dissipation ? w pd = p internal + p i / o th05 p internal internal power dissipation ? w p internal = i dd x v dd (1) th06 p i / o i/o power dissipation ? w p i / o = ? (i ol * v ol ) + ? (i oh * (v dd - v oh )) th07 p der derated power ? w p der = pd max (t j - t a )/ ? ja (2) note 1: i dd is current to run the chip alone without driving any load on the output pins. 2: t a = ambient temperature. 3: t j = junction temperature.
? 2013 microchip technology inc. preliminary ds41674b-page 221 PIC12LF1552 21.7 timing parameter symbology the timing parameter symbols have been created with one of the following formats: figure 21-3: load conditions 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc clkin ck clkout rd rd cs cs rw rd or wr di sdix sc sckx do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance v ss c l legend: c l = 50 pf for all pins load condition pin
PIC12LF1552 ds41674b-page 222 preliminary ? 2013 microchip technology inc. 21.8 ac characteristics: PIC12LF1552-i/e figure 21-4: clock timing clkin clkout q4 q1 q2 q3 q4 q1 os02 os03 (clkout mode) note 1: see table 21-3 . os11 os12
? 2013 microchip technology inc. preliminary ds41674b-page 223 PIC12LF1552 table 21-1: clock oscillator timing requirements table 21-2: oscillator parameters standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions os01 f osc external clkin frequency (1) dc ? 0.5 mhz ec oscillator mode (low) dc ? 4 mhz ec oscillator mode (medium) dc ? 20 mhz ec oscillator mode (high) os02 t osc external clkin period (1) 50 ? ? ns ec mode os03 t cy instruction cycle time (1) 200 ? dc ns t cy = f osc /4 * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at ?min? values with an external clock applied to clkin pin. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions os08 hf osc internal calibrated hfintosc frequency (1) ? 16.0 ? mhz 0c ? t a ? +85c os08a hf tol frequency tolerance ? ? 3 ? % 25c, 16mhz ? ? 6?%0c ? t a ? +85c, 16 mh z os09 lf osc internal lfintosc frequency ? 31 ? khz -40c ? t a ? +125c os10* t iosc st hfintosc wake-up from sleep start-up time ?5 8 ? s * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: to ensure these oscillator frequency tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended.
PIC12LF1552 ds41674b-page 224 preliminary ? 2013 microchip technology inc. figure 21-5: clkout and i/o timing table 21-3: clkout and i/o timing parameters standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions os11 tosh2ckl f osc ? to clkout ? (1) ??70nsv dd = 3.3-3.6v os12 tosh2ckh f osc ? to clkout ? (1) ??72nsv dd = 3.3-3.6v os13 tckl2iov clkout ? to port out valid (1) ??20ns os14 tiov2ckh port input valid before clkout ? (1) t osc + 200 ns ? ? ns os15 tosh2iov fosc ? (q1 cycle) to port out valid ? 50 70* ns v dd = 3.3-3.6v os16 tosh2ioi fosc ? (q2 cycle) to port input invalid (i/o in hold time) 50 ? ? ns v dd = 3.3-3.6v os17 tiov2osh port input valid to fosc ?? (q2 cycle) (i/o in setup time) 20 ? ? ns os18* tior port output rise time (2) ?1532nsv dd = 2.0v os19* tiof port output fall time (2) ?2855nsv dd = 2.0v os20* tinp int pin input high or low time 25 ? ? ns os21* tioc interrupt-on-change new input level time 25 ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25 ? c unless otherwise stated. note 1: measurements are taken in ec mode where clkout output is 4 x t osc . f osc clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 os11 os19 os13 os15 os18, os19 os20 os21 os17 os16 os14 os12 os18 old value new value write fetch read execute cycle
? 2013 microchip technology inc. preliminary ds41674b-page 225 PIC12LF1552 figure 21-6: reset, watchdog timer, os cillator start-up timer and power-up timer timing figure 21-7: brown-out rese t timing and characteristics v dd mclr internal por pwrt time-out internal reset (1) watchdog timer 33 30 31 34 i/o pins 34 note 1: asserted low. reset (1) v bor v dd (device in brown-out reset) (device not in brown-out reset) 33 (1) note 1: 64 ms delay only if pwrte bit in the configuration words is programmed to ? 0 ?. 2 ms delay if pwrte = 0 and vregen = 1 . reset (due to bor) v bor and v hyst 37
PIC12LF1552 ds41674b-page 226 preliminary ? 2013 microchip technology inc. table 21-4: reset, watchdog timer, oscill ator start-up timer, power-up timer and brown-out reset parameters figure 21-8: timer0 ex ternal clock timings standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions 30 t mc lmclr pulse width (low) 2 5 ? ? ? ? ? s ? s -40c to +85c +85c to +125c 31 t wdtlp low-power watchdog timer time-out period 10 16 27 ms v dd = 3.3v-3.6v, 1:16 prescaler used 33* t pwrt power-up timer period, pwrte = 0 40 65 140 ms 34* t ioz i/o high-impedance from mclr low or watchdog timer reset ??2.0 ? s 35 v bor brown-out reset voltage (1) 2.55 1.80 2.70 1.90 2.85 2.05 v v borv = 0 borv = 1 36* v hyst brown-out reset hysteresis 0 25 50 mv -40c to +85c 37* t bordc brown-out reset dc response time 135 ? sv dd ? v bor * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: to ensure these voltage tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended. t0cki t1cki 40 41 42 45 46 47 49 tmr0
? 2013 microchip technology inc. preliminary ds41674b-page 227 PIC12LF1552 table 21-5: timer0 external clock requirements table 21-6: PIC12LF1552 a/d converter (adc) characteristics : (1,2,3) standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions 40* t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 41* t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 42* t t 0p t0cki period greater of: 20 or t cy + 40 n ? ? ns n = prescale value (2, 4, ..., 256) 45* t t 1h t1cki high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note 1: for proper operation, the minimum value of the adc positive voltage reference must be 1.8v or greater. standard operating conditions (unless otherwise stated) operating temperature tested at 25c param no. sym. characteristic min. typ? max. units conditions ad01 n r resolution ? ? 10 bit ad02 e il integral error ? 0.5 1 lsb -40c to +85c, ? v ref ? 2.0v ad03 e dl differential error ? 0.4 1 lsb -40c to +85c, ? v ref ? 2.0v ad04 e off offset error ? 0.4 2 lsb -40c to +85c, ? v ref ? 2.0v ad05 e gn gain error ? 0.3 2 lsb -40c to +85c, ? v ref ? 2.0v ad06 v ref reference voltage range (vrefh ? vrefl) 1.8 2.0 ? ? ? ? v v absolute minimum minimum for 1lsb accuracy ad07 v ain full-scale range v ss ?v ref v ad08 z ain recommended impedance of analog voltage source ?? 3k ? can go higher if external 0.01 ? f capacitor is present on input pin. * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: total absolute error includes integral, differential, offset and gain errors. 2: the adc conversion result never decreases with an increase in the input voltage and has no missing codes. 3: when adc is off, it will not consume any current other than leakage current. the power-down current specification includes any such leakage from the adc module. 4: adc reference voltage (ref+) is the selected reference input, v ref + pin, v dd pin or the fvr buffer1. when the fvr is selected as the reference input, the fvr buffer1 output selection must be 2.048v, (adfvr<1:0> = 10 ).
PIC12LF1552 ds41674b-page 228 preliminary ? 2013 microchip technology inc. table 21-7: PIC12LF1552 adc conversion requirements figure 21-9: PIC12LF1552 adc conv ersion timing (normal mode) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions ad130* t ad adc clock period 0.7 0.7 ? ? 25 8 ? s ? s t osc -based, -40c to +85c t osc -based, +85c to +125c adc internal frc oscillator period 1.0 1.6 6.0 ? s adcs<1:0> = 11 (adfrc mode) ad131 t cnv conversion time (not including acquisition time) (1) ?11?t ad set go/done bit to conversion complete ad132* t acq acquisition time ? 5.0 ? ? s * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the adres register may be read on the following t cy cycle. ad131 ad130 bsf adcon0, go q4 adc clk adc data adres adif go sample old_data sampling stopped done new_data 987 3210 note 1: if the adc clock source is selected as frc, a time of t cy is added before the adc clock starts. this allows the sleep instruction to be executed. 1 t cy 6 ad134 (t osc /2 (1) ) 1 t cy ad132
? 2013 microchip technology inc. preliminary ds41674b-page 229 PIC12LF1552 figure 21-10: PIC12LF1552 adc conversion timing (sleep mode) table 21-8: digital-to-analog conv erter (dac) specifications ad132 ad131 ad130 bsf adcon0, go q4 adc clk adc data adres adif go sample old_data sampling stopped done new_data 9 7 3210 note 1: if the adc clock source is selected as frc, a time of t cy is added before the adc clock starts. this allows the sleep instruction to be executed. ad134 6 8 1 t cy (t osc /2 + t cy (1) ) 1 t cy operating conditions: 2.5v < v dd < 5.5v, -40c < t a < +125c (unless otherwise stated). param no. sym. characteristics min. typ. max. units comments dac01* c lsb step size ? v dd /32 ? v dac02* c acc absolute accuracy ? ? ? 1/2 lsb dac03* c r unit resistor value (r) ? 5000 ? ? dac04* c st settling time (1) ??10 ? s * these parameters are characterized but not tested. note 1: settling time measured while dacr<4:0> transitions from ? 0000 ? to ? 1111 ?.
PIC12LF1552 ds41674b-page 230 preliminary ? 2013 microchip technology inc. notes:
? 2013 microchip technology inc. preliminary ds41674b-page 231 PIC12LF1552 22.0 dc and ac characteristics graphs and charts graphs and charts are not available at this time.
PIC12LF1552 ds41674b-page 232 preliminary ? 2013 microchip technology inc. notes:
? 2013 microchip technology inc. preliminary ds41674b-page 233 PIC12LF1552 23.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c ? for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families ? simulators - mplab sim software simulator ?emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstration/development boards, evaluation kits, and starter kits 23.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
PIC12LF1552 ds41674b-page 234 preliminary ? 2013 microchip technology inc. 23.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 23.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c compilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 23.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 23.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 23.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility
? 2013 microchip technology inc. preliminary ds41674b-page 235 PIC12LF1552 23.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 23.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 23.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is microchip?s most cost effective high-speed hardware debugger/programmer for microchip flash digital signal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 23.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer?s pc using a full speed usb interface and can be connected to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software.
PIC12LF1552 ds41674b-page 236 preliminary ? 2013 microchip technology inc. 23.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environment (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the application. when halted at a break- point, the file registers can be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 23.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an mmc card for file storage and data applications. 23.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits.
? 2013 microchip technology inc. preliminary ds41674b-page 237 PIC12LF1552 24.0 packaging information 24.1 package marking information * standard picmicro ? device marking consists of microchip part number, year code, week code and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 8-lead soic (3.90 mm) example nnn 8-lead pdip (300 mil) example xxxxxxxx xxxxxnnn yyww 12f1552 3 e e/p 1210 12f1552 e/sn1210 017 017
PIC12LF1552 ds41674b-page 238 preliminary ? 2013 microchip technology inc. package marking information (continued) 8-lead msop (3x3 mm) example l1552i 210017 8-lead udfn (2x3x0.5 mm) example baq 210 10
? 2013 microchip technology inc. preliminary ds41674b-page 239 PIC12LF1552 24.2 package details the following sections give the technical details of the packages. n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c
PIC12LF1552 ds41674b-page 240 preliminary ? 2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2013 microchip technology inc. preliminary ds41674b-page 241 PIC12LF1552 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
PIC12LF1552 ds41674b-page 242 preliminary ? 2013 microchip technology inc.
? 2013 microchip technology inc. preliminary ds41674b-page 243 PIC12LF1552 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
PIC12LF1552 ds41674b-page 244 preliminary ? 2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2013 microchip technology inc. preliminary ds41674b-page 245 PIC12LF1552 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
PIC12LF1552 ds41674b-page 246 preliminary ? 2013 microchip technology inc.
? 2013 microchip technology inc. preliminary ds41674b-page 247 PIC12LF1552
PIC12LF1552 ds41674b-page 248 preliminary ? 2013 microchip technology inc. appendix a: data sheet revision history revision a(12/2012) original release. revision b (01/2013) revised product id system ? corrected packaged code mf to mu.
? 2013 microchip technology inc. preliminary ds41674b-page 249 PIC12LF1552 notes:
PIC12LF1552 ds41674b-page 250 preliminary ? 2013 microchip technology inc. index a aadacq register............................................................. 133 aadcap register ............................................................. 134 aadcon0 register .................................................... 25, 128 aadcon1 register .................................................... 25, 129 aadcon2 register .................................................... 25, 130 aadcon3 register .......................................................... 131 aadgrd register ............................................................ 133 aadpre register ............................................................. 132 aadres0h register .......................................................... 25 aadres0l register ........................................................... 25 aadres1h register .......................................................... 25 aadres1l register ........................................................... 25 aadresxh register (adfm = 0) ............................. 135, 136 aadresxl register (adfm = 0) ............................. 135, 136 aadstat register ........................................................... 132 absolute maximum ratings .............................................. 213 ac characteristics industrial and extended ............................................ 222 load conditions ........................................................ 221 ackstat.......................................................................... 178 ackstat status flag ...................................................... 178 adc................................................................................... 105 acquisition requirements ......................................... 115 associated registers.................................................. 117 block diagram........................................................... 105 calculating acquisition time..................................... 115 channel selection ..................................................... 106 configuration............................................................. 106 configuring interrupt ................................................. 110 conversion clock...................................................... 106 conversion procedure .............................................. 110 internal sampling switch (r ss ) impedance .............. 115 interrupts................................................................... 108 operation .................................................................. 109 operation during sleep ............................................ 109 port configuration ..................................................... 106 reference voltage (v ref )......................................... 106 source impedance .................................................... 115 special event trigger................................................ 109 specifications .................................................... 227, 228 starting an adc conversion..................................... 108 adcon0 register....................................................... 23, 111 adcon1 register....................................................... 23, 112 adcon2 register............................................................... 23 addfsr ........................................................................... 203 addwfc .......................................................................... 203 adres0h register............................................................. 23 adres0h register (adfm = 0) ....................................... 113 adres0h register (adfm = 1) ....................................... 114 adres0l register ............................................................. 23 adres0l register (adfm = 0)........................................ 113 adres0l register (adfm = 1)........................................ 114 alternate pin function......................................................... 92 analog-to-digital converter. see adc ansela register................................................................ 95 apfcon register............................................................... 92 assembler mpasm assembler ................................................... 234 automatic context saving................................................... 61 b bank 14 ............................................................................... 25 bank 2................................................................................. 23 bank 3................................................................................. 24 bank 31............................................................................... 26 bank 4................................................................................. 24 bank 5................................................................................. 24 bank 6................................................................................. 24 bank 7................................................................................. 25 bank 8-13 ........................................................................... 25 bf ............................................................................. 178, 180 bf status flag .......................................................... 178, 180 block diagrams adc .......................................................................... 105 adc transfer function ............................................. 116 analog input model................................................... 116 clock source .............................................................. 41 generic i/o port.......................................................... 91 hardware cvd.......................................................... 120 interrupt logic............................................................. 57 on-chip reset circuit................................................. 49 PIC12LF1552 ........................................................... 3, 8 timer0 ...................................................................... 138 voltage reference .................................................... 101 borcon register.............................................................. 51 bra .................................................................................. 204 brown-out reset (bor)...................................................... 51 specifications ........................................................... 226 timing and characteristics ....................................... 225 c c compilers mplab c18 .............................................................. 234 call................................................................................. 205 callw ............................................................................. 205 clock sources external modes........................................................... 42 ec....................................................................... 42 internal modes ............................................................ 43 hfintosc ......................................................... 43 internal oscillator clock switch timing .............. 44 lfintosc.......................................................... 43 clock switching .................................................................. 46 code examples adc conversion ....................................................... 110 hardware cvd conversion ...................................... 126 initializing porta....................................................... 91 writing to flash program memory .............................. 84 config1 register ............................................................. 36 config2 register ............................................................. 37 core function register....................................................... 22 customer change notification service............................. 254 customer notification service .......................................... 254 customer support............................................................. 254 d data memory ...................................................................... 15 dc and ac characteristics............................................... 231 dc characteristics extended and industrial ............................................ 218 industrial and extended ............................................ 214 development support ....................................................... 233 device configuration .......................................................... 35 code protection .......................................................... 38 configuration word..................................................... 35 user id ................................................................. 38, 39
? 2013 microchip technology inc. preliminary ds41674b-page 251 PIC12LF1552 device id register .............................................................. 39 device overview ............................................................. 7, 71 digital-to-analog converter (dac) specifications............................................................ 229 e electrical specifications .................................................... 213 enhanced mid-range cpu................................................. 11 errata .................................................................................... 5 extended instruction set addfsr ................................................................... 203 f firmware instructions........................................................ 199 fixed voltage reference (fvr) ........................................ 101 associated registers ................................................ 102 flash program memory ...................................................... 75 associated registers .................................................. 90 configuration word w/ flash program memory.......... 90 erasing........................................................................ 79 modifying..................................................................... 85 write verify ................................................................. 87 writing......................................................................... 81 flash program memory control .......................................... 75 fsr register ...................................................................... 22 fvrcon (fixed voltage reference control) register ..... 102 h hardware capacitive voltage divider. see hardware cvd hardware cvd.................................................................. 119 acquisition timer ...................................................... 121 additional sample and hold capacitor ..................... 123 analog bus visibility.................................................. 123 associated registers.................................................. 137 block diagram........................................................... 120 completion of a conversion...................................... 121 double sample conversion ...................................... 122 guard ring outputs .................................................. 122 operation .................................................................. 121 pre-charge timer ...................................................... 121 starting a conversion ............................................... 121 terminating a conversion......................................... 121 i i 2 c mode (mssp1) acknowledge sequence timing................................ 182 bus collision during a repeated start condition ................... 187 during a stop condition.................................... 188 effects of a reset...................................................... 183 i 2 c clock rate w/brg.............................................. 190 master mode operation .......................................................... 174 reception.......................................................... 180 start condition timing .............................. 176, 177 transmission .................................................... 178 multi-master communication, bus collision and arbitration ......................................................... 183 multi-master mode .................................................... 183 read/write bit information (r/w bit) ........................ 159 slave mode transmission .................................................... 164 sleep operation ........................................................ 183 stop condition timing............................................... 182 indf register ..................................................................... 22 indirect addressing ............................................................. 30 instruction format............................................................. 200 instruction set................................................................... 199 addlw..................................................................... 203 addwf .................................................................... 203 addwfc.................................................................. 203 andlw..................................................................... 203 andwf .................................................................... 203 bra .......................................................................... 204 call......................................................................... 205 callw ..................................................................... 205 lslf ......................................................................... 207 lsrf ........................................................................ 207 movf ....................................................................... 207 moviw ..................................................................... 208 movlb ..................................................................... 208 movwi ..................................................................... 209 option.................................................................... 209 reset...................................................................... 209 subwfb .................................................................. 211 tris ......................................................................... 212 bcf .......................................................................... 204 bsf........................................................................... 204 btfsc...................................................................... 204 btfss ...................................................................... 204 call......................................................................... 205 clrf ........................................................................ 205 clrw ....................................................................... 205 clrwdt .................................................................. 205 comf ....................................................................... 205 decf........................................................................ 205 decfsz ................................................................... 206 goto ....................................................................... 206 incf ......................................................................... 206 incfsz..................................................................... 206 iorlw...................................................................... 206 iorwf...................................................................... 206 movlw .................................................................... 208 movwf.................................................................... 208 nop.......................................................................... 209 retfie..................................................................... 210 retlw ..................................................................... 210 return................................................................... 210 rlf........................................................................... 210 rrf .......................................................................... 211 sleep ...................................................................... 211 sublw..................................................................... 211 subwf..................................................................... 211 swapf..................................................................... 212 xorlw .................................................................... 212 xorwf .................................................................... 212 intcon register................................................................ 62 internal oscillator block intosc specifications ................................................... 223 internal sampling switch (r ss ) impedance ..................... 115 internet address ............................................................... 254 interrupt-on-change........................................................... 97 associated registers................................................ 100 interrupts ............................................................................ 57 adc .......................................................................... 110 associated registers w/ interrupts .............................. 67 intosc specifications ..................................................... 223 iocaf register .................................................................. 99 iocan register .................................................................. 99 iocap register .................................................................. 99
PIC12LF1552 ds41674b-page 252 preliminary ? 2013 microchip technology inc. l lata register..................................................................... 95 load conditions ................................................................ 221 lslf.................................................................................. 207 lsrf ................................................................................. 207 m master synchronous serial port. see mssp1 mclr .................................................................................. 52 internal ........................................................................ 52 memory organization.......................................................... 13 data ............................................................................ 15 program ...................................................................... 13 microchip internet web site .............................................. 254 moviw.............................................................................. 208 movlb.............................................................................. 208 movwi.............................................................................. 209 mplab asm30 assembler, linker, librarian ................... 234 mplab integrated development environment software .. 233 mplab pm3 device programmer..................................... 236 mplab real ice in-circuit emulator system................. 235 mplink object linker/mplib object librarian ................ 234 mssp1 .............................................................................. 143 i 2 c mode................................................................... 154 i 2 c mode operation .................................................. 156 spi mode .................................................................. 146 sspbuf register ..................................................... 149 sspsr register ....................................................... 149 o opcode field descriptions ............................................. 199 option ............................................................................ 209 option register .............................................................. 140 osccon register .............................................................. 47 oscillator associated registers .................................................. 48 oscillator module ........... ..................................................... 41 ech ............................................................................ 41 ecl ............................................................................. 41 ecm ............................................................................ 41 intosc ...................................................................... 41 oscillator parameters.................. ..................... .......... ....... 223 oscillator specifications .................................................... 223 oscillator start-up timer (ost) specifications............................................................ 226 oscstat register............................................................. 48 p packaging ......................................................................... 237 marking ............................................................. 237, 238 pcl and pclath ............................................................... 11 pcl register....................................................................... 22 pclath register................................................................ 22 pcon register ............................................................. 23, 55 pie1 register ................................................................ 23, 63 pie2 register ................................................................ 23, 64 pir1 register................................................................ 23, 65 pir2 register................................................................ 23, 66 pmadr registers ............................................................... 75 pmadrh registers ............................................................ 75 pmadrl register............................................................... 88 pmadrl registers ............................................................. 75 pmcon1 register ........................................................ 75, 89 pmcon2 register ........................................................ 75, 90 pmdath register............................................................... 88 pmdatl register............................................................... 88 pmdrh register ................................................................ 88 porta ............................................................................... 93 ansela register ....................................................... 93 associated registers .................................................. 96 lata register ............................................................ 23 porta register ......................................................... 23 specifications ........................................................... 224 porta register ................................................................. 94 power-down mode (sleep)................................................. 69 associated registers .................................................. 70 power-on reset .................................................................. 50 power-up time-out sequence ............................................ 52 power-up timer (pwrt) .................................................... 50 specifications ........................................................... 226 program memory ................................................................ 13 map and stack............................................................ 13 map and stack (PIC12LF1552 ................................... 14 programming, device instructions .................................... 199 r reader response............................................................. 255 read-modify-write operations ......................................... 199 registers aadacq (hardware cvd acquisition time control) 133 aadcap (hardware cvd additional sample capacitor selection).......................................................... 134 aadcon0 (hardware cvd control 0) ..................... 128 aadcon1 (hardware cvd control 1) ..................... 129 aadcon2 (hardware cvd control 2) ..................... 130 aadcon3 (hardware cvd control 3) ..................... 131 aadgrd (hardware cvd guard ring control)....... 133 aadpre (hardware cvd pre-charge control) ....... 132 aadresxh (hardware cvd result high) with adfm = 0) ................................................ 135, 136 aadresxl (hardware cvd result low) with adfm = 0) ................................................ 135, 136 aadstat (hardware cvd status) .......................... 132 adcon0 (adc control 0) ........................................ 111 adcon1 (adc control 1) ........................................ 112 adres0h (adc result high) with adfm = 0) ........ 113 adres0h (adc result high) with adfm = 1) ........ 114 adres0l (adc result low) with adfm = 0).......... 113 adres0l (adc result low) with adfm = 1).......... 114 ansela (porta analog select)............................... 95 apfcon (alternate pin function control) ................. 92 borcon brown-out reset control) .......................... 51 configuration word 1.................................................. 36 configuration word 2.................................................. 37 core function, summary............................................ 22 device id .................................................................... 39 fvrcon................................................................... 102 intcon (interrupt control)......................................... 62 iocaf (interrupt-on-change porta flag)................ 99 iocan (interrupt-on-change porta negative edge)................................................... 99 iocap (interrupt-on-change porta positive edge) 99 lata (data latch porta)......................................... 95 option_reg (option) ......................................... 140 osccon (oscillator control) ..................................... 47 oscstat (oscillator status) ..................................... 48 pcon (power control register)................................. 55 pcon (power control) ............................................... 55 pie1 (peripheral interrupt enable 1)........................... 63 pie2 (peripheral interrupt enable 2)........................... 64 pir1 (peripheral interrupt register 1) ........................ 65
? 2013 microchip technology inc. preliminary ds41674b-page 253 PIC12LF1552 pir2 (peripheral interrupt request 2) ........................ 66 pmadrl (program memory address)........................ 88 pmcon1 (program memory control 1)...................... 89 pmcon2 (program memory control 2)...................... 90 pmdath (program memory data) ............................. 88 pmdatl (program memory data).............................. 88 pmdrh (program memory address) ......................... 88 porta........................................................................ 94 special function, summary ........................................ 23 sspadd (mssp1 address and baud rate, i 2 c mode) ......................................................... 196 sspcon1 (mssp1 control 1).................................. 193 sspcon2 (ssp control 2)....................................... 194 sspcon3 (ssp control 3)....................................... 195 sspmsk (ssp mask)............................................... 196 sspstat (ssp status)............................................ 191 status...................................................................... 16 trisa (tri-state porta)........................................... 94 wdtcon (watchdog timer control) ......................... 73 wpua (weak pull-up porta) ................................... 96 reset .............................................................................. 209 reset................................................................................... 49 reset instruction ................................................................. 52 resets................................................................................. 49 associated registers .................................................. 56 revision history ................................................................ 248 s software simulator (mplab sim)..................................... 235 special event trigger........................................................ 109 special function registers (sfrs)..................................... 23 spi mode (mssp1) associated registers ................................................ 153 spi clock .................................................................. 149 sspadd register............................................................. 196 sspcon1 register .......................................................... 193 sspcon2 register .......................................................... 194 sspcon3 register .......................................................... 195 sspmsk register............................................................. 196 sspov.............................................................................. 180 sspov status flag .......................................................... 180 sspstat register ........................................................... 191 r/w bit...................................................................... 159 stack ................................................................................... 28 accessing.................................................................... 28 reset........................................................................... 30 stack overflow/underflow................................................... 52 status register ............................................................... 16 subwfb........................................................................... 211 t temperature indicator associated registers ................................................ 104 temperature indicator module .......................................... 103 thermal considerations.................................................... 220 timer0............................................................................... 138 associated registers ................................................ 140 operation .................................................................. 138 specifications............................................................ 227 timing diagrams acknowledge sequence ........................................... 182 adc conversion ....................................................... 228 adc conversion (sleep mode)................................. 229 baud rate generator with clock arbitration ............. 175 brg reset due to sda arbitration during start condition........................................................... 186 brown-out reset (bor)............................................ 225 brown-out reset situations ........................................ 51 bus collision during a repeated start condition (case 1)............................................................ 187 bus collision during a repeated start condition (case 2)............................................................ 187 bus collision during a start condition (scl = 0) ..... 185 bus collision during a stop condition (case 1)....... 188 bus collision during a stop condition (case 2)....... 188 bus collision during start condition (sda only) ...... 185 bus collision for transmit and acknowledge ........... 184 clkout and i/o ...................................................... 224 clock synchronization .............................................. 172 clock timing............................................................. 222 first start bit timing ................................................. 176 i 2 c master mode (7 or 10-bit transmission) ............ 179 i 2 c master mode (7-bit reception) .......................... 181 i 2 c stop condition receive or transmit mode......... 183 int pin interrupt ......................................................... 60 internal oscillator switch timing ................................ 45 repeat start condition ............................................. 177 reset start-up sequence ........................................... 53 reset, wdt, ost and power-up timer ................... 225 spi mode (master mode) ......................................... 149 timer0 external clock .............................................. 226 wake-up from interrupt............................................... 70 timing parameter symbology .......................................... 221 tmr0 register.................................................................... 23 tris ................................................................................. 212 trisa register............................................................. 23, 94 v v ref . s ee adc reference voltage w wake-up using interrupts ................................................... 70 watchdog timer (wdt)...................................................... 52 associated registers.................................................. 74 modes......................................................................... 72 specifications ........................................................... 226 wcol ....................................................... 175, 178, 180, 182 wcol status flag.................................... 175, 178, 180, 182 wdtcon register ............................................................. 73 wpua register................................................................... 96 write protection .................................................................. 38 www address ................................................................. 254 www, on-line support ................................................... 2, 5
PIC12LF1552 ds41674b-page 254 preliminary ? 2013 microchip technology inc. the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
? 2013 microchip technology inc. preliminary ds41674b-page 255 PIC12LF1552 reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41674b PIC12LF1552 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
PIC12LF1552 ds41674b-page 256 preliminary ? 2013 microchip technology inc. notes:
? 2013 microchip technology inc. preliminary ds41674b-page 257 PIC12LF1552 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: PIC12LF1552 tape and reel option: blank = standard packaging (tube or tray) t = tape and reel (1) temperature range: i= -40 ? c to +85 ? c(industrial) e= -40 ? c to +125 ? c (extended) package: (2) mu = micro lead frame (dfn) 2x3 ms = msop p=plastic dip sn = soic pattern: qtp, sqtp, code or special requirements (blank otherwise) examples: a) PIC12LF1552t - i/sn tape and reel, industrial temperature, soic package b) PIC12LF1552 - i/p industrial temperature pdip package c) PIC12LF1552 - e/mu extended temperature, dfn package note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. 2: small form-factor packaging options may be available. please check www.microchip.com/packaging for small- form factor package availability, or contact your local sa les office. [x] (1) tape and reel option -
PIC12LF1552 ds41674b-page 258 preliminary ? 2013 microchip technology inc. notes:
? 2013 microchip technology inc. preliminary ds41674b-page 259 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, application maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620769461 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal me thods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications c ontained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
ds41674b-page 260 preliminary ? 2013 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-2819-3187 fax: 86-571-2819-3189 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 11/29/12

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